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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
MacDonald; James R.
Address:
Buda, TX
No. of patents:
30
Patents:












Patent Number Title Of Patent Date Issued
8572420 Power managed USB for computing applications using a controller October 29, 2013
In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer co
7685450 Power management of computer peripheral devices which determines non-usage of a device through u March 23, 2010
A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the
7310498 Communication protocol for personal computer system human interface devices over a low bandwidth December 18, 2007
A system and method for maintaining communications with a radio frequency (RF) peripheral device such as an RF input device and an RF output device. A computer may search for an RF peripheral device by transmitting a signal request on available channels until a response is received from
7222252 Power management of computer peripheral devices which determines non-usage of a device through u May 22, 2007
A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the
6825786 Associative noise attenuation November 30, 2004
A system may include a memory configured to store an attenuation waveform and control logic. The control logic is configured to receive a synchronizing signal indicative of an operating characteristic of a noise source. In response to a value of a characteristic (e.g., frequency) of
6550059 Method for generating optimized vector instructions from high level programming languages April 15, 2003
A method for compiling source code to produce vector instructions, wherein parallel operands are placed in adjacent locations in memory and wherein the realignment of the operands is minimized. One embodiment generates two-element vector instructions from generalized (e.g., non-loop) sou
6484193 Fully pipelined parallel multiplier with a fast clock cycle November 19, 2002
A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a multiplier and a multiplicand.
6295574 Real time interrupt handling for superscalar processors September 25, 2001
A CPU includes a real time interrupt (RTI) control unit configured to control real time interrupt capabilities of the CPU. Upon receipt of a real time interrupt signal via an RTI pin, the RTI control unit interrupts the currently executing instructions at an instruction boundary in order
6044430 Real time interrupt handling for superscalar processors March 28, 2000
A CPU includes a real time interrupt (RTI) control unit configured to control real time interrupt capabilities of the CPU. Upon receipt of a real time interrupt signal via an RTI pin, the RTI control unit interrupts the currently executing instructions at an instruction boundary in order
5946497 System and method for providing microprocessor serialization using programmable fuses August 31, 1999
A system and method for providing a microprocessor with a software accessible serial number. A plurality of programmable fuses on the processor are encoded with a value representative of a serial number. Circuitry is provided on the processor for transferring the value encoded on the
5933620 Method and apparatus for serializing microprocessor identification numbers August 3, 1999
A method and apparatus for providing a microprocessor serial number. A small, nonvolatile random access memory is packaged with the CPU die to provide a storage space for a CPU serial number which can be programmed before leaving the factory. Both the CPU die and the nonvolatile RAM die
5913224 Programmable cache including a non-lockable data way and a lockable data way configured to lock June 15, 1999
A computer system is disclosed which provides for execution of real-time code from cache memory. A cache management unit provides the real-time code to the cache memory from system memory upon a initiation of a read operation by a processor. Once in cache memory, the processor executes t
5905898 Apparatus and method for storing interrupt source information in an interrupt controller based u May 18, 1999
A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt
5894577 Interrupt controller with external in-service indication for power management within a computer April 13, 1999
An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower prio
5799203 System for receiving peripheral device capability information and selectively disabling correspo August 25, 1998
A system and method for providing information regarding system support capabilities to a processor. A computer system includes a processing unit, a main memory and a first plurality of peripherals coupled to a first bus. A bus bridge couples the first bus to a second bus and a second plu
5790783 Method and apparatus for upgrading the software lock of microprocessor August 4, 1998
A method and apparatus for providing, maintaining and upgrading the software lock of a microprocessor. When a processor upgrade occurs, software that was serialized to the previously installed processor detects that it is running on an unauthorized processor. The software initiates a
5790663 Method and apparatus for software access to a microprocessor serial number August 4, 1998
A method and apparatus for software to access a microprocessor serial number. Provision of the serial number allows the manufacturer better control over its product and also permits software vendors to register their products. The serial number is encrypted using a pair of encryption
5784627 Integrated timer for power management and watchdog functions July 21, 1998
A variety of clock intensive functions, such as interval timers, real-time clocks, and resettable timers for triggering watchdog reset and power management mode transitions, are provided using a single counter and timer event control logic. Such an integrated timer provides multiple time
5774544 Method an apparatus for encrypting and decrypting microprocessor serial numbers June 30, 1998
A method and apparatus for encrypting and decrypting a microprocessor serial number. First and second encryption keys and a serial number are provided in microprocessor machine specific registers. The serial number is encrypted using the first key. The encrypted serial number is encrypte
5768584 ROM chip enable encoding method and computer system employing the same June 16, 1998
A non-volatile memory chip enable encoding method allows the storage of both boot code and user application software within a common memory array. The chip enable encoding method further allows a variable number of memory banks to be provided within the non-volatile memory array and allo
5765003 Interrupt controller optimized for power management in a computer system or subsystem June 9, 1998
An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower prio
5696927 Memory paging system and method including compressed page mapping hierarchy December 9, 1997
A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes pa
5640573 Power management message bus for integrated processor June 17, 1997
An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, int
5630099 Non-volatile memory array controller capable of controlling memory banks having variable bit wid May 13, 1997
A non-volatile memory controller is provided which is connectable directly to the local bus of a computer system and which allows access to one or more 32-bit banks of ROM and to an 8-bit bank of non-volatile memory. The 8-bit bank of non-volatile memory may be used, for example, to stor
5623673 System management mode and in-circuit emulation memory mapping and locking method April 22, 1997
A computer system is provided that includes an interrupt driven system management mode during which system management code is accessed. In one embodiment, a lock-out register is provided to prevent accesses to the system management code while the computer system is operating in its n
5600839 System and method for controlling assertion of a peripheral bus clock signal through a slave dev February 4, 1997
A system and method for controlling a peripheral bus clock signal through a slave device are provided that accommodate a power conservation scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. Prior to stopping t
5561821 System for performing I/O access and memory access by driving address of DMA configuration regis October 1, 1996
A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O
5561819 Computer system selecting byte lane for a peripheral device during I/O addressing technique of d October 1, 1996
A direct memory access controller implements a two-cycle approach for performing a desired DMA transfer by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines
5557757 High performance integrated processor architecture including a sub-bus control unit for generati September 17, 1996
An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between
5493684 Power management architecture including a power management messaging bus for conveying an encode February 20, 1996
An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, int










 
 
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