| Patent Number |
Title Of Patent |
Date Issued |
| 7608855 |
Polymer dielectrics for memory element array interconnect |
October 27, 2009 |
| Disclosed are semiconductor devices containing a polymer dielectric and at least one active device containing an organic semiconductor material and a passive layer. Also disclosed are semiconductor devices further containing a conductive polymer. Such devices are characterized by light |
| 7427457 |
Methods for designing grating structures for use in situ scatterometry to detect photoresist def |
September 23, 2008 |
| The present invention discloses a system and method for designing grating structures for use in situ scatterometry during the photolithography process to detect a photoresist defect (e.g., photoresist erosion, pattern collapse or pattern bending). In one embodiment, a grating structu |
| 7268066 |
Method for semiconductor gate line dimension reduction |
September 11, 2007 |
| To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely |
| 7169711 |
Method of using carbon spacers for critical dimension (CD) reduction |
January 30, 2007 |
| A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposi |
| 7125652 |
Immersion lithographic process using a conforming immersion medium |
October 24, 2006 |
| A method of making a device using a lithographic system having a lens from which an exposure pattern is emitted. A conforming immersion medium can be positioned between a photo resist layer and the lens. The photo resist layer, which can be disposed over a wafer, and the lens can be brou |
| 7122455 |
Patterning with rigid organic under-layer |
October 17, 2006 |
| For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimensio |
| 7115440 |
SO.sub.2 treatment of oxidized CuO for copper sulfide formation of memory element growth |
October 3, 2006 |
| Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve oxidizing a portion of a copper containing electrode to form a copper oxide layer; contacting the copper oxide layer with at least one of a sulfur containing gas or pla |
| 7112489 |
Negative resist or dry develop process for forming middle of line implant layer |
September 26, 2006 |
| A method of implanting a middle of line (MOL) implant layer of a flash memory device that does not require a descumming step is disclosed. In a first embodiment, the method includes depositing a negative tone resist over the MOL implant layer. Portions of the negative tone resist in and |
| 7056804 |
Shallow trench isolation polish stop layer for reduced topography |
June 6, 2006 |
| A method of making and shallow trench isolation feature including 1) providing a semiconductor substrate, 2) forming a polish stop layer over the semiconductor substrate, 3) forming a nitride containing layer over the polish stop layer, 4) forming a shallow trench layer through a por |
| 7052921 |
System and method using in situ scatterometry to detect photoresist pattern integrity during the |
May 30, 2006 |
| The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of ph |
| 7018922 |
Patterning for elongated V.sub.SS contact flash memory |
March 28, 2006 |
| A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gat |
| 7015504 |
Sidewall formation for high density polymer memory element array |
March 21, 2006 |
| Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side |
| 7011762 |
Metal bridging monitor for etch and CMP endpoint detection |
March 14, 2006 |
| One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the met |
| 7008832 |
Damascene process for a T-shaped gate electrode |
March 7, 2006 |
| A damascene process can be utilized to form a T-shaped gate. A silicon rich nitride or SiON layer can be etched to form a first aperture. An oxide layer can be provided above the silicon rich nitride layer or SiON layer. A second aperture or trench can be provided in the oxide layer. |
| 6989332 |
Ion implantation to modulate amorphous carbon stress |
January 24, 2006 |
| A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of |
| 6982043 |
Scatterometry with grating to observe resist removal rate during etch |
January 3, 2006 |
| Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photore |
| 6972576 |
Electrical critical dimension measurement and defect detection for reticle fabrication |
December 6, 2005 |
| A system for testing a reticle used in semiconductor wafer fabrication is provided. The system includes a reticle that has an opaque metal layer over a translucent substrate. The reticle includes one or more test features containing probe points operable for electrical contact. The s |
| 6955939 |
Memory element formation with photosensitive polymer dielectric |
October 18, 2005 |
| A method of making organic memory devices containing organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The organic memory devices are made using a patternable, photosensitive dielectric that facilitates formation of |
| 6906777 |
Pellicle for a lithographic lens |
June 14, 2005 |
| A method and apparatus for preventing contamination in a lithographic apparatus including a projection system, including providing the lithographic apparatus including the projection system for imaging an irradiated portion of a mask onto a target portion of a substrate and placing a |
| 6900124 |
Patterning for elliptical Vss contact on flash memory |
May 31, 2005 |
| A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gat |
| 6878961 |
Photosensitive polymeric memory elements |
April 12, 2005 |
| A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer |
| 6869888 |
E-beam flood exposure of spin-on material to eliminate voids in vias |
March 22, 2005 |
| A method for forming a semiconductor device is described. The method comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. The BARC layer is |
| 6869734 |
EUV reflective mask having a carbon film and a method of making such a mask |
March 22, 2005 |
| An exemplary embodiment relates to a mask for integrated circuit fabrication equipment. The mask includes a multilayer film and an amorphous carbon layer above the multilayer film. The multilayer film is at least partially relatively reflective to radiation having a wavelength of les |
| 6864556 |
CVD organic polymer film for advanced gate patterning |
March 8, 2005 |
| A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a patt |
| 6864024 |
Real-time control of chemically-amplified resist processing on wafer |
March 8, 2005 |
| One aspect of the present invention relates to a system and method for controlling environmental acid scavengers in real time during pattern exposure of a chemically amplified resist-clad wafer. The system includes a semiconductor wafer comprising a chemically amplified resist layer |
| 6852455 |
Amorphous carbon absorber/shifter film for attenuated phase shift mask |
February 8, 2005 |
| An exemplary embodiment relates to a phase shifting mask including a glass substrate layer and an amorphous carbon absorber layer located above the glass substrate layer. The amorphous carbon absorber layer includes apertures through which light passes unaltered to the glass substrate |
| 6849530 |
Method for semiconductor gate line dimension reduction |
February 1, 2005 |
| To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely |
| 6836398 |
System and method of forming a passive layer by a CMP process |
December 28, 2004 |
| The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is p |
| 6829040 |
Lithography contrast enhancement technique by varying focus with wavelength modulation |
December 7, 2004 |
| A projection lithography system exposes a photo sensitive material on a surface of a semiconductor substrate that includes surface height variations between a high level and a low level. The system comprises an illumination source projecting illumination within a narrow wavelength ba |
| 6825114 |
Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patternin |
November 30, 2004 |
| A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed |
| 6825060 |
Photosensitive polymeric memory elements |
November 30, 2004 |
| A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer |
| 6808591 |
Model based metal overetch control |
October 26, 2004 |
| A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch cha |
| 6803267 |
Silicon containing material for patterning polymeric memory element |
October 12, 2004 |
| The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, a |
| 6790790 |
High modulus filler for low k materials |
September 14, 2004 |
| Disclosed are methods for processing a low k material involving providing a low k material layer comprising one or more low k polymer materials and one or more high modulus fillers on a semiconductor substrate, and chemical mechanical polishing the low k material layer so as to remove a |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6773998 |
Modified film stack and patterning strategy for stress compensation and prevention of pattern di |
August 10, 2004 |
| A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The |
| 6773954 |
Methods of forming passive layers in organic memory cells |
August 10, 2004 |
| Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode |
| 6771356 |
Scatterometry of grating structures to monitor wafer stress |
August 3, 2004 |
| A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The |
| 6764949 |
Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabric |
July 20, 2004 |
| A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The |
| 6753266 |
Method of enhancing gate patterning properties with reflective hard mask |
June 22, 2004 |
| An exemplary method of fabricating an integrated circuit can include depositing a reflective metal material layer over a layer of polysilicon, depositing an anti-reflective coating over the reflective metal material layer, trim etching the anti-reflective coating to form a pattern, etchi |
| 6740566 |
Ultra-thin resist shallow trench process using high selectivity nitride etch |
May 25, 2004 |
| In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra- |
| 6737222 |
Dual damascene process utilizing a bi-layer imaging layer |
May 18, 2004 |
| A method of utilizing a multilayer photoresist to form contact holes and/or conductors utilizing a dual damascene process includes utilizing layered photoresists. A contact in a conductive line can be formed in a single deposition step or in a two-stage deposition step. Image layers can |
| 6689541 |
Process for forming a photoresist mask |
February 10, 2004 |
| In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a |
| 6686270 |
Dual damascene trench depth monitoring |
February 3, 2004 |
| One aspect of the present invention relates to a method of dual damascene processing, involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material; and simultaneously (i) forming a plurality of trenches in the insulation |
| 6684172 |
Sensor to predict void free films using various grating structures and characterize fill perform |
January 27, 2004 |
| One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitorin |
| 6660645 |
Process for etching an organic dielectric using a silyated photoresist mask |
December 9, 2003 |
| A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched |
| 6656763 |
Spin on polymers for organic memory devices |
December 2, 2003 |
| A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin- |
| 6654660 |
Controlling thermal expansion of mask substrates by scatterometry |
November 25, 2003 |
| One aspect of the present invention relates to a system and method for controlling thermal expansion on an EUV mask during EUV photolithography. The system includes an EUV photolithography system for irradiating one or more layers of a wafer through one or more gratings of a patterned EU |
| 6654659 |
Quartz crystal monitor wafer for lithography and etch process monitoring |
November 25, 2003 |
| One aspect of the present invention relates to a feedback-driven, closed loop system/method for obtaining consistently formed semiconductor structures. The system/method involves controlling the progression of a lithography process such as a deposition or etching process. The system |
| 6635409 |
Method of strengthening photoresist to prevent pattern collapse |
October 21, 2003 |
| There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then treated to change its material properties before the pho |
