| Patent Number |
Title Of Patent |
Date Issued |
| 7554914 |
System and method for adaptively balancing network traffic over router output ports |
June 30, 2009 |
| A method and system for determining an output port upon which to transmit a packet in a router having a plurality of output ports adapted to be coupled with an adjacent router. In one embodiment, a list is created of output ports that are coupled with the adjacent router, and the list is |
| 7525904 |
Redundant packet routing and switching device and method |
April 28, 2009 |
| A router and method therefore for routing and switching a packet from an incoming link to an outgoing link. The router may include a plurality of network processing units, a plurality of switching engines, and a plurality of connections between the plurality of network processing uni |
| 7453883 |
Method for compressing route data in a router |
November 18, 2008 |
| A method for a router having a routing table and a forwarding table. In an embodiment, the method includes creating an entry for use in the forwarding table, the entry corresponding to multiple entries of the routing table. The entry may correspond to a set of entries of the routing |
| 7450438 |
Crossbar apparatus for a forwarding table memory in a router |
November 11, 2008 |
| A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of stages to a secto |
| 6317810 |
Microprocessor having a prefetch cache |
November 13, 2001 |
| A central processing unit of a computer includes a single-ported data cache and a dual-ported prefetch cache. The data cache accommodates a first pipeline and the prefetch cache, which is much smaller than the data cache, accommodates both the first pipeline and a second pipeline. If a |
| 6164840 |
Ensuring consistency of an instruction cache with a store cache check and an execution blocking |
December 26, 2000 |
| A method of ensuring instruction cache consistency in a processor includes executing a flush instruction whenever a program executed by the processor stores data to a given data address and, subsequently, executes another instruction requiring a data fetch from the same address. Accordin |
| 6078587 |
Mechanism for coalescing non-cacheable stores |
June 20, 2000 |
| Data is collected from multiple data packets for group transfer on a data path so as to maximize utilization of the data path. A particularly suitable data path is one that is coupled to transfer data to a graphics frame buffer. In collecting data from multiple data packets, data from |
| 6076147 |
Non-inclusive cache system using pipelined snoop bus |
June 13, 2000 |
| A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which is absent from the external cache. A pipelined snoop bus is ported to each of the set of |
| 6061766 |
Non-inclusive cache method using pipelined snoop bus |
May 9, 2000 |
| A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which is absent from the external cache. A pipelined snoop bus is ported to each of the set of |
| 6016532 |
Method for handling data cache misses using help instructions |
January 18, 2000 |
| A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help |
| 5900018 |
Processor-implemented method of controlling data access to shared resource via exclusive access |
May 4, 1999 |
| An atomic instruction is executed without the use of a dedicated atomic unit. A store instruction is transmitted from a front-end of one of a plurality of processors to a write-cache to cause the write-cache to obtain exclusive access to a control memory of a shared resource. A first |
| 5878252 |
Microprocessor configured to generate help instructions for performing data cache fills |
March 2, 1999 |
| A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help |
