| Patent Number |
Title Of Patent |
Date Issued |
| 7623387 |
Non-volatile storage with early source-side boosting for reducing program disturb |
November 24, 2009 |
| Non-volatile storage with reduced program disturb is provided by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a |
| 7623386 |
Reducing program disturb in non-volatile storage using early source-side boosting |
November 24, 2009 |
| Program disturb is reduced in non-volatile storage by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a first boost mo |
| 7616499 |
Retention margin program verification |
November 10, 2009 |
| Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence an |
| 7616481 |
Memories with alternate sensing techniques |
November 10, 2009 |
| The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to |
| 7615445 |
Methods of reducing coupling between floating gates in nonvolatile memory |
November 10, 2009 |
| A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structu |
| 7606074 |
Word line compensation in non-volatile memory erase operations |
October 20, 2009 |
| Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select ga |
| 7577026 |
Source and drain side early boosting using local self boosting for non-volatile storage |
August 18, 2009 |
| Program disturb is reduced during programming of non-volatile storage by providing a boosting scheme in which isolation voltage are applied to two word lines to create a source side channel region on a source side of one isolation word line, an intermediate channel region between the iso |
| 7545681 |
Segmented bitscan for verification of programming |
June 9, 2009 |
| A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to |
| 7512014 |
Comprehensive erase verification for non-volatile memory |
March 31, 2009 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
| 7508720 |
Systems for comprehensive erase verification in non-volatile memory |
March 24, 2009 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
| 7504686 |
Self-aligned non-volatile memory cell |
March 17, 2009 |
| Floating gate structures are disclosed that have a projection that extends away from the surface of a substrate. This projection may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the word line extends downwar |
| 7468918 |
Systems for programming non-volatile memory with reduced program disturb by removing pre-charge |
December 23, 2008 |
| Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselec |
| 7468911 |
Non-volatile memory using multiple boosting modes for reduced program disturb |
December 23, 2008 |
| A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switc |
| 7463532 |
Comprehensive erase verification for non-volatile memory |
December 9, 2008 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
| 7463531 |
Systems for programming non-volatile memory with reduced program disturb by using different pre- |
December 9, 2008 |
| Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselec |
| 7463522 |
Non-volatile storage with boosting using channel isolation switching |
December 9, 2008 |
| Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line befo |
| 7460406 |
Alternate sensing techniques for non-volatile memories |
December 2, 2008 |
| The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to |
| 7460404 |
Boosting for non-volatile storage using channel isolation switching |
December 2, 2008 |
| Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before |
| 7450435 |
Systems for comprehensive erase verification in non-volatile memory |
November 11, 2008 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
| 7450433 |
Word line compensation in non-volatile memory erase operations |
November 11, 2008 |
| Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select ga |
| 7450430 |
Programming non-volatile memory with reduced program disturb by using different pre-charge enabl |
November 11, 2008 |
| Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselec |
| 7440323 |
Reducing program disturb in non-volatile memory using multiple boosting modes |
October 21, 2008 |
| A method for operating a non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be |
| 7440319 |
Apparatus with segmented bitscan for verification of programming |
October 21, 2008 |
| A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to |
| 7436019 |
Non-volatile memory cells shaped to increase coupling to word lines |
October 14, 2008 |
| A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. The upper |
| 7433241 |
Programming non-volatile memory with reduced program disturb by removing pre-charge dependency o |
October 7, 2008 |
| Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselec |
| 7414894 |
Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transc |
August 19, 2008 |
| A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the readi |
| 7405968 |
Non-volatile memory cell using high-K material and inter-gate programming |
July 29, 2008 |
| A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielec |
| 7355237 |
Shield plate for limiting cross coupling between floating gates |
April 8, 2008 |
| A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set |
| 7349264 |
Alternate sensing techniques for non-volatile memories |
March 25, 2008 |
| The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to |
| 7286406 |
Method for controlled programming of non-volatile memory exhibiting bit line coupling |
October 23, 2007 |
| The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the |
| 7253055 |
Pillar cell flash memory technology |
August 7, 2007 |
| An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer |
| 7230854 |
Method for programming non-volatile memory with self-adjusting maximum program loop |
June 12, 2007 |
| The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elem |
| 7218552 |
Last-first mode and method for programming of non-volatile memory with reduced program disturb |
May 15, 2007 |
| A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word |
| 7215575 |
Detecting over programmed memory |
May 8, 2007 |
| In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some |
| 7206235 |
Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling |
April 17, 2007 |
| The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the |
| 7206231 |
System for programming non-volatile memory with self-adjusting maximum program loop |
April 17, 2007 |
| The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elem |
| 7183153 |
Method of manufacturing self aligned non-volatile memory cells |
February 27, 2007 |
| A method of forming an array of non-volatile memory cells includes forming a plurality of floating gate structures and shaping the plurality of floating gate structures to reduce the width of upper parts of floating gate structures. A first process forms floating gates by etching an uppe |
| 7177199 |
Behavior based programming of non-volatile memory |
February 13, 2007 |
| The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are |
| 7170788 |
Last-first mode and apparatus for programming of non-volatile memory with reduced program distur |
January 30, 2007 |
| A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word |
| 7161836 |
Method for programming non-volatile memory with self-adjusting maximum program loop |
January 9, 2007 |
| The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elem |
| 7154779 |
Non-volatile memory cell using high-k material inter-gate programming |
December 26, 2006 |
| A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielec |
| 7057931 |
Flash memory programming using gate induced junction leakage current |
June 6, 2006 |
| A method for programming a storage element and a storage element programmed using gate induced junction leakage current are provided. The element may include at least a floating gate on a substrate, an active region in the substrate, and a second gate adjacent to the floating gate. T |
| 7049652 |
Pillar cell flash memory technology |
May 23, 2006 |
| An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer |
| 7046555 |
Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transc |
May 16, 2006 |
| A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the readi |
| 7023737 |
System for programming non-volatile memory with self-adjusting maximum program loop |
April 4, 2006 |
| The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elem |
| 7009889 |
Comprehensive erase verification for non-volatile memory |
March 7, 2006 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
| 6975537 |
Source side self boosting technique for non-volatile memory |
December 13, 2005 |
| A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source |
| 6917542 |
Detecting over programmed memory |
July 12, 2005 |
| In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some |
| 6914823 |
Detecting over programmed memory after further programming |
July 5, 2005 |
| In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some |
| 6859397 |
Source side self boosting technique for non-volatile memory |
February 22, 2005 |
| A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source |
