| Patent Number |
Title Of Patent |
Date Issued |
| 7618866 |
Structure and method to form multilayer embedded stressors |
November 17, 2009 |
| A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically |
| 7595233 |
Gate stress engineering for MOSFET |
September 29, 2009 |
| Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon |
| 7572712 |
Method to form selective strained Si using lateral epitaxy |
August 11, 2009 |
| Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is |
| 7566609 |
Method of manufacturing a semiconductor structure |
July 28, 2009 |
| There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes |
| 7564081 |
finFET structure with multiply stressed gate electrode |
July 21, 2009 |
| A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress wh |
| 7553709 |
MOSFET with body contacts |
June 30, 2009 |
| A semiconductor structure includes a metal oxide semiconductor field effect transistor that includes a body contact region that extends from body region located beneath a channel region that separates a pair of source/drain regions within the metal oxide semiconductor field effect tr |
| 7550330 |
Deep junction SOI MOSFET with enhanced edge body contacts |
June 23, 2009 |
| A semiconductor structure is provided that has body contacts that are located at the edges of the device channel and a buried insulating region under the device channel that is shallower than the buried insulating regions under the source/drain junctions. A method of forming such a s |
| 7541629 |
Embedded insulating band for controlling short-channel effect and leakage reduction for DSB proc |
June 2, 2009 |
| A method and structure for reducing leakage currents in integrated circuits based on a direct silicon bonding (DSB) fabrication process. After recessing a top semiconductor layer and an underlying semiconductor substrate, a dielectric layer may be deposited and etched back to form em |
| 7504696 |
CMOS with dual metal gate |
March 17, 2009 |
| Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that is complementary to a |
| 7501651 |
Test structure of semiconductor device |
March 10, 2009 |
| A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semi |
| 7485524 |
MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating |
February 3, 2009 |
| The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are ep |
| 7485516 |
Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offse |
February 3, 2009 |
| A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from th |
| 7482656 |
Method and structure to form self-aligned selective-SOI |
January 27, 2009 |
| Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate |
| 7473608 |
N-channel MOSFETs comprising dual stressors, and methods for forming the same |
January 6, 2009 |
| The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semicon |
| 7442619 |
Method of forming substantially L-shaped silicide contact for a semiconductor device |
October 28, 2008 |
| A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, t |
| 7442586 |
SOI substrate and SOI device, and method for forming the same |
October 28, 2008 |
| An improved semiconductor-on-insulator (SOI) substrate is provided, which has a substantially planar upper surface and comprises at least first and second patterned buried insulator layers. Specifically, the first patterned buried insulator layer has a first thickness and is located in |
| 7413961 |
Method of fabricating a transistor structure |
August 19, 2008 |
| The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of fo |
| 7410852 |
Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect tran |
August 12, 2008 |
| An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region ad |
| 7393751 |
Semiconductor structure including laminated isolation region |
July 1, 2008 |
| A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolation trench; (2) a U |
| 7385258 |
Transistors having v-shape source/drain metal contacts |
June 10, 2008 |
| A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconduc |
| 7317204 |
Test structure of semiconductor device |
January 8, 2008 |
| A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which ar |
| 7309901 |
Field effect transistors (FETs) with multiple and/or staircase silicide |
December 18, 2007 |
| A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and |
| 7279758 |
N-channel MOSFETs comprising dual stressors, and methods for forming the same |
October 9, 2007 |
| The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor |
| 7220662 |
Fully silicided field effect transistors |
May 22, 2007 |
| Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, |
| 7112481 |
Method for forming self-aligned dual salicide in CMOS technologies |
September 26, 2006 |
| A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for |
| 7105440 |
Self-forming metal silicide gate for CMOS devices |
September 12, 2006 |
| A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or |
| 7067368 |
Method for forming self-aligned dual salicide in CMOS technologies |
June 27, 2006 |
| A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for |
| 7064025 |
Method for forming self-aligned dual salicide in CMOS technologies |
June 20, 2006 |
| A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for |
