| Patent Number |
Title Of Patent |
Date Issued |
| 7374654 |
Method of making an organic memory cell |
May 20, 2008 |
| A method of making an organic memory cell which comprises two electrodes with a controllably conductive media between the two electrodes is disclosed. The present invention involves providing a dielectric layer having formed therein one or more first electrode pads; removing a portio |
| 7323418 |
Etch-back process for capping a polymer memory device |
January 29, 2008 |
| The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides |
| 7226856 |
Nano-electrode-array for integrated circuit interconnects |
June 5, 2007 |
| An integrated circuit and a method of manufacturing an integrated circuit is provided including providing an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is formed over the dielectric layer in the trench and via, and a conductor is dep |
| 7169706 |
Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper depositio |
January 30, 2007 |
| An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor |
| 7151018 |
Method and apparatus for transistor sidewall salicidation |
December 19, 2006 |
| A method for manufacturing a transistor is provided. The transistor has a substrate with an insulator on the substrate. A structure on the insulator having a structure sidewall is provided with spacers covering a portion of the structure sidewall. An exposed portion of the structure |
| 7115440 |
SO.sub.2 treatment of oxidized CuO for copper sulfide formation of memory element growth |
October 3, 2006 |
| Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve oxidizing a portion of a copper containing electrode to form a copper oxide layer; contacting the copper oxide layer with at least one of a sulfur containing gas or pla |
| 7064065 |
Silver under-layers for electroless cobalt alloys |
June 20, 2006 |
| In one embodiment, a method for depositing a capping layer on a substrate surface containing a copper layer is provided which includes exposing the substrate surface to a zinc solution, exposing the substrate surface to a silver solution to form a silver layer thereon and depositing the |
| 7015504 |
Sidewall formation for high density polymer memory element array |
March 21, 2006 |
| Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side |
| 6992004 |
Implanted barrier layer to improve line reliability and method of forming same |
January 31, 2006 |
| A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided |
| 6982188 |
Post CMP precursor treatment |
January 3, 2006 |
| Systems and methods are disclosed for creating smooth surfaces for layers that are employed in memory cells and have previously been subject to a CMP process. The present invention employs various cycles of exposing the post CMP surface to inorganic and organic acids, as well as growing |
| 6972254 |
Manufacturing a conformal atomic liner layer in an integrated circuit interconnect |
December 6, 2005 |
| A manufacturing method for an integrated circuit has a substrate with a semiconductor device thereon. A channel dielectric layer is deposited over the device and has an opening provided therein. A reducing process is performed in order to reduce the oxidation on the conductor and a c |
| 6900488 |
Multi-cell organic memory element and methods of operating and fabricating |
May 31, 2005 |
| The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of th |
| 6893955 |
Manufacturing seedless barrier layers in integrated circuits |
May 17, 2005 |
| An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barri |
| 6893895 |
CuS formation by anodic sulfide passivation of copper surface |
May 17, 2005 |
| Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve passivating a portion of a copper containing electrode to form a copper sulfide layer in an electrochemical cell by applying a current through a passivation solution |
| 6861349 |
Method of forming an adhesion layer with an element reactive with a barrier layer |
March 1, 2005 |
| A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a |
| 6836398 |
System and method of forming a passive layer by a CMP process |
December 28, 2004 |
| The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is p |
| 6835655 |
Method of implanting copper barrier material to improve electrical performance |
December 28, 2004 |
| A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper |
| 6815340 |
Method of forming an electroless nucleation layer on a via bottom |
November 9, 2004 |
| A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and formin |
| 6803267 |
Silicon containing material for patterning polymeric memory element |
October 12, 2004 |
| The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, a |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6773954 |
Methods of forming passive layers in organic memory cells |
August 10, 2004 |
| Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode |
| 6770905 |
Implantation for the formation of CuX layer in an organic memory device |
August 3, 2004 |
| An organic memory cell having a CuX layer made by implantation is disclosed. The organic memory cell is made of two electrodes, at least one containing copper, with a controllably conductive media between the two electrodes. The controllably conductive media contains an organic semic |
| 6746971 |
Method of forming copper sulfide for memory cell |
June 8, 2004 |
| An organic memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The controllably conductive media changes its impedance when an ext |
| 6724087 |
Laminated conductive lines and methods of forming the same |
April 20, 2004 |
| A method of fabricating an integrated circuit can include forming a laminated conductive line. The laminated conductive line can be formed in a dielectric trench. The laminated conductive line can include alternating barrier layers and copper layers. An integrated circuit includes at lea |
| 6703308 |
Method of inserting alloy elements to reduce copper diffusion and bulk diffusion |
March 9, 2004 |
| A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a |
| 6703307 |
Method of implantation after copper seed deposition |
March 9, 2004 |
| A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and forming an implanted layer proximate and conformal to the barrier layer and th |
| 6686263 |
Selective formation of top memory electrode by electroless formation of conductive materials |
February 3, 2004 |
| The present invention provides systems and methods that facilitate formation and use of organic memory devices. An electroless plating process is employed that operates at relatively low temperatures and without employing electrical current. The electroless process is utilized to for |
| 6589408 |
Non-planar copper alloy target for plasma vapor deposition systems |
July 8, 2003 |
| A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a |
| 6583051 |
Method of manufacturing an amorphized barrier layer for integrated circuit interconnects |
June 24, 2003 |
| A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited |
| 6555909 |
Seedless barrier layers in integrated circuits and a method of manufacture therefor |
April 29, 2003 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein |
| 6555171 |
Cu/Sn/Pd activation of a barrier layer for electroless CU deposition |
April 29, 2003 |
| Provided herein is a method of utilizing electroless copper deposition to form interconnects in a semiconductor device. An opening is formed in a dielectric layer in the form of a trench, via or combination thereof, and a diffusion barrier layer is blanket deposited in the opening. Then, |
| 6538327 |
Method of copper interconnect formation using atomic layer copper deposition and a device thereb |
March 25, 2003 |
| A method for fabricating a semiconductor interconnect structure having a substrate with an interconnect structure patterned therein, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer, and a device thereby formed. The barrier layer is formed |
| 6534865 |
Method of enhanced fill of vias and trenches |
March 18, 2003 |
| A manufacturing method and apparatus for filling vias and trenches in integrated circuits is provided having a substrate with a device provided thereon. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a |
| 6528884 |
Conformal atomic liner layer in an integrated circuit interconnect |
March 4, 2003 |
| A manufacturing method, and an integrated circuit resulting therefrom has a substrate with a semiconductor device thereon. A channel dielectric layer is deposited over the device and has an opening provided therein. A reducing process is performed in order to reduce the oxidation on the |
| 6518648 |
Superconductor barrier layer for integrated circuit interconnects |
February 11, 2003 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A high temperature superconductor material barrier layer lines the o |
| 6504251 |
Heat/cold amorphized barrier layer for integrated circuit interconnects |
January 7, 2003 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening. An amorphized layer is formed by |
| 6501177 |
Atomic layer barrier layer for integrated circuit interconnects |
December 31, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening and has a first amorphized atomic |
| 6489683 |
Variable grain size in conductors for semiconductor vias and trenches |
December 3, 2002 |
| A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to |
| 6479902 |
Semiconductor catalytic layer and atomic layer deposition thereof |
November 12, 2002 |
| A semiconductor and manufacturing method is provided for device interconnects with a catalytic layer of copper, palladium, nickel, cobalt, silver, or other catalytic material deposited in a atomic layer by atomic layer epitaxy on a barrier layer of tantalum, titanium, tungsten, their |
| 6465867 |
Amorphous and gradated barrier layer for integrated circuit interconnects |
October 15, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A |
| 6455415 |
Method of encapsulated copper (Cu) interconnect formation |
September 24, 2002 |
| A method of forming a semiconductor device having selectively fabricated copper interconnect structure that is encapsulated within selectively formed metallic barriers. An exemplary encapsulated copper interconnect structure includes a first low dielectric constant layer (low K1) formed |
| 6426297 |
Differential pressure chemical-mechanical polishing in integrated circuit interconnects |
July 30, 2002 |
| A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor wafer and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and a |
| 6403466 |
Post-CMP-Cu deposition and CMP to eliminate surface voids |
June 11, 2002 |
| A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrie |
| 6368965 |
Method for low stress plating of semiconductor vias and channels |
April 9, 2002 |
| A method is provided for forming conductive layers in semiconductor device channels and vias by using forward current and periodic pulse reverses for filling inward from the sidewalls of the channels and vias. The pulse reversals and inward filling reduce recrystallization rate to improv |
| 6368961 |
Graded compound seed layers for semiconductors |
April 9, 2002 |
| A method is provided for forming semiconductor copper seed layers with the copper alloyed with one of the metals from the group comprising tin, magnesium, and aluminum. The alloy further has a graded nitrogen content with the highest concentration of nitrogen proximate a tungsten nitride |
| 6368954 |
Method of copper interconnect formation using atomic layer copper deposition |
April 9, 2002 |
| A semiconductor interconnect structure having a substrate with an interconnect structure patterned thereon, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer. A process for creating such structures is described. The barrier layer is forme |
| 6348732 |
Amorphized barrier layer for integrated circuit interconnects |
February 19, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is de |
| 6346472 |
Manufacturing method for semiconductor metalization barrier |
February 12, 2002 |
| A semiconductor metalization barrier, and manufacturing method therefor, is provided which is deposited from an aqueous solution containing the Period 4 transition metals of chromium, nickel, and copper deposited on a palladium-activated copper bonding pad. |
| 6344410 |
Manufacturing method for semiconductor metalization barrier |
February 5, 2002 |
| A semiconductor metalization barrier, and manufacturing method therefor, is provided which is a stack of a cobalt layer and cobalt tungsten layer deposited on a copper bonding pad. |
| 6340633 |
Method for ramped current density plating of semiconductor vias and trenches |
January 22, 2002 |
| A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to |
