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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Longcor; Steven W.
Address:
Mountain View, CA
No. of patents:
48
Patents:












Patent Number Title Of Patent Date Issued
8062942 Method for fabricating multi-resistive state memory devices November 22, 2011
A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive ele
8003511 Memory cell formation using ion implant isolated conductive metal oxide August 23, 2011
Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive meta
7889539 Multi-resistive state memory device with conductive oxide electrodes February 15, 2011
A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electr
7884349 Selection device for re-writable memory February 8, 2011
A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across th
7832090 Method of making a planar electrode November 16, 2010
Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction re
7633790 Multi-resistive state memory device with conductive oxide electrodes December 15, 2009
A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electr
7528405 Conductive memory stack with sidewall May 5, 2009
A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi
7457147 Two terminal memory array having reference cells November 25, 2008
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7439082 Conductive memory stack with non-uniform width October 21, 2008
A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has
7400006 Conductive memory device with conductive oxide electrodes July 15, 2008
A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a
7394679 Multi-resistive state element with reactive metal July 1, 2008
A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive ele
7382645 Two terminal memory array having reference cells June 3, 2008
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7382644 Two terminal memory array having reference cells June 3, 2008
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7330370 Enhanced functionality in a two-terminal memory array February 12, 2008
A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory eleme
7326979 Resistive memory device with a treated interface February 5, 2008
A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory propertie
7227775 Two terminal memory array having reference cells June 5, 2007
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7186569 Conductive memory stack with sidewall March 6, 2007
A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi
7180772 High-density NVRAM February 20, 2007
A cross point array and peripheral circuitry that accesses the cross point array. The peripheral circuitry receives a supply voltage of approximately 1.8 volts or less, generates voltages of a magnitude not more than approximately 3 volts, and senses current that is indicative of a n
7095643 Re-writable memory with multiple memory layers August 22, 2006
A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing
7082052 Multi-resistive state element with reactive metal July 25, 2006
A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive ele
7079442 Layout of driver sets in a cross point memory array July 18, 2006
Layouts of driver sets in a cross point memory array. Since both terminals of a memory cell in a cross point structure are typically used for selection purposes, dedicated driver sets are typically required for both x and y directions. By fabricating the cross point array above the drive
7075817 Two terminal memory array having reference cells July 11, 2006
A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry comp
7071008 Multi-resistive state material that uses dopants July 4, 2006
A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally dop
7067862 Conductive memory device with conductive oxide electrodes June 27, 2006
A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a
7057914 Cross point memory array with fast access time June 6, 2006
Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if th
7042035 Memory array with high temperature wiring May 9, 2006
A memory array with components that can withstand high temperature fabrication is provided. Some memory materials require high temperature process steps in order to achieve desired properties. During fabrication, a memory material is deposited on structures that may include metal lines
7038935 2-terminal trapped charge memory device with voltage switchable multi-level resistance May 2, 2006
A 2-terminal trapped charge memory device is disclosed with voltage switchable multi-level resistance. The trapped charge memory device has a trapped charge memory body sandwiched between two electrodes. The trapped charge memory body can be made of a variety of semiconducting or ins
7020012 Cross point array using distinct voltages March 28, 2006
Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely defined. Additionally,
7009909 Line drivers that use minimal metal layers March 7, 2006
Line drivers that use minimal metal layers. Line driver connections typically need to be made to various other peripheral circuits. Although multiple metal layers could be used to make all the necessary connections, it is desirable to use the fewest metal layers possible. By keeping
7009235 Conductive memory stack with non-uniform width March 7, 2006
A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has
6972985 Memory element having islands December 6, 2005
A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are
6970375 Providing a reference voltage to a cross point memory array November 29, 2005
Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array in order to prevent unselected conductive array lines from floating to an undes
6965137 Multi-layer conductive memory device November 15, 2005
A multilayered conductive memory device capable of storing information individually or as part of an array of memory devices is provided. Boundary control issues at the interface between layers of the device due to the use of incompatible materials can be avoided by intentionally dop
6917539 High-density NVRAM July 12, 2005
High density NVRAM. An array of memory cells capable of storing at least a megabit of information, each memory cell including a memory plug that includes a memory element that switches from a first resistance state to a second resistance state upon application of a first write voltage of
6909632 Multiple modes of operation in a cross point array June 21, 2005
Multiple modes of operation in a cross point array. The invention is a cross point array that uses a read voltage across a conductive array line pair during a read mode. The read voltage produces a read current that is indicative of a first program state when the read current is at a fir
6906939 Re-writable memory with multiple memory layers June 14, 2005
A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing lo
6870755 Re-writable memory with non-linear memory element March 22, 2005
A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of t
6850429 Cross point memory array with memory plugs exhibiting a characteristic hysteresis February 1, 2005
Providing a cross point, memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantiall
6834008 Cross point memory array using multiple modes of operation December 21, 2004
Cross point memory array using multiple modes of operation. The invention is a cross point memory array that uses a read mode to determine the resistive state of a memory plug, a first write mode to cause the memory plug to change from a first resistive state to a second resistive state,
6831854 Cross point memory array using distinct voltages December 14, 2004
Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines uniquely defining a single memory plug
6798685 Multi-output multiplexor September 28, 2004
Providing a multi-output multiplexor. The invention is multi-output multiplexor that, depending on the control signals, allows various modulating circuits to pass no voltage, pass some voltage or pass all the voltage on one of the multiplexor's ports. A modulating circuit can be full
6731544 Method and apparatus for multiple byte or page mode programming of a flash memory array May 4, 2004
A memory array contains memory cells designed to be erased using Fowler-Nordheim ("FN") tunneling through the channel area, and programmed using either channel hot electron injection ("CHE") or channel-initiated secondary electron injection ("CISEI"). To reduce disturbance of the flo
5973374 Flash memory array having well contact structures October 26, 1999
A common source flash memory array providing multiple well contact structures distributed within the array without the need for separate well tap regions connected to dedicated channel lines. The contact locations between Vss metal common source lines and source bus regions are used to
5680345 Nonvolatile memory cell with vertical gate overlap and zero birds beaks October 21, 1997
A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of fie
5661055 Method of making nonvolatile memory cell with vertical gate overlap and zero birds' beaks August 26, 1997
A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of fie
5552331 Process for self-aligned source for high density memory September 3, 1996
An improved method for protecting the gate edge and adjacent source region of a semiconductor device is disclosed. In this method, spacers are formed along the gates of one type of transistor to protect the gate edge and adjacent source area during a self-aligned source etch. Spacers of
5151381 Method for local oxidation of silicon employing two oxidation steps September 29, 1992
A process of forming field oxide regions using a field oxidation performed in a dry oxidation environment in a temperature equal to or greater than approximately 1000.degree. C. The dry oxidation reduces or eliminates the formation of Kooi ribbons, and the high temperature field oxidatio
4987465 Electro-static discharge protection device for CMOS integrated circuit inputs January 22, 1991
An ESD protection device for CMOS integrated circuit inputs is disclosed. Two clamp components, coupled by a current limiting device, couple the pad to the circuitry of the chip. The device prevents damage to the circuit from an ESD of approximately 8000 or more volts at an input termina










 
 
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