| Patent Number |
Title Of Patent |
Date Issued |
| 7626869 |
Multi-phase wordline erasing for flash memory |
December 1, 2009 |
| Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi |
| 7619932 |
Algorithm for charge loss reduction and Vt distribution improvement |
November 17, 2009 |
| Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of |
| 7573103 |
Back-to-back NPN/PNP protection diodes |
August 11, 2009 |
| A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and elec |
| 7561457 |
Select transistor using buried bit line from core |
July 14, 2009 |
| A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in t |
| 7553727 |
Using implanted poly-1 to improve charging protection in dual-poly process |
June 30, 2009 |
| The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the |
| 7394702 |
Methods for erasing and programming memory devices |
July 1, 2008 |
| A dual-bit memory device includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory can be provided in which electrons can be injected into the charge storage regions to erase the charge storage regi |
| 7285827 |
Back-to-back NPN/PNP protection diodes |
October 23, 2007 |
| A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device. |
| 7269067 |
Programming a memory device |
September 11, 2007 |
| A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias |
| 7262095 |
System and method for reducing process-induced charging |
August 28, 2007 |
| A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate. |
| 7167398 |
System and method for erasing a memory cell |
January 23, 2007 |
| A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and era |
