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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Liu; Peichun
Address:
Austin, TX
No. of patents:
6
Patents:












Patent Number Title Of Patent Date Issued
7590774 Method and system for efficient context swapping September 15, 2009
Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage loc
6822486 Multiplexer methods and apparatus November 23, 2004
In a first aspect, a method is provided for selecting a signal from a plurality of signals. The method includes the steps of (1) providing a plurality of multiplexers, each multiplexer configured to selectively output one of a plurality of signals input by the multiplexer using an ou
6721874 Method and system for dynamically shared completion table supporting multiple threads in a proce April 13, 2004
A method and system for utilizing a completion table in a superscalar processor is disclosed. The method and system comprises providing a plurality of threads to the processor and associating a link list with each of the threads, wherein each entry associated with a thread is linked
6463514 Method to arbitrate for a cache block October 8, 2002
A method of arbitrating between cache access circuits (i.e., load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a second cache address. The stalling is performed in response to a comparison of one or more
6064245 Dynamic circuit for capturing data with wide reset tolerance May 16, 2000
The present invention is directed to an apparatus for precharging complementary data circuits. The apparatus comprises two hold circuits, one for storing the data and the other for storing its complement. A signal for initiates precharging the hold circuits to the same signal level,
5604879 Single array address translator with segment and page invalidate ability and method of operation February 18, 1997
A CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the effective-to-real-address-translator (ERAT) has two CAM fields (ESID, EPI) that independently compare an inpu










 
 
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