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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lin; Yai-Fen
Address:
Non-Tour, TW
No. of patents:
19
Patents:












Patent Number Title Of Patent Date Issued
7001809 Method to increase coupling ratio of source to floating gate in split-gate flash February 21, 2006
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6753569 Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolati June 22, 2004
A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a "smiling" gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls
6724036 Stacked-gate flash memory cell with folding gate and increased coupling ratio April 20, 2004
A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the
6674118 PIP capacitor for split-gate flash process January 6, 2004
A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, res
6635922 Method to fabricate poly tip in split gate flash October 21, 2003
A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the mini
6465841 Split gate flash memory device having nitride spacer to prevent inter-poly oxide damage October 15, 2002
A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers s
6410957 Method of forming poly tip to improve erasing and programming speed in split gate flash June 25, 2002
A method is disclosed for forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve the erasing and programming speed of the cell. The method involves the use of an oxide other than the poly oxide that is conventionally employed in formin
6380583 Method to increase coupling ratio of source to floating gate in split-gate flash April 30, 2002
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6358796 Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolati March 19, 2002
A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a "smiling" gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls
6355527 Method to increase coupling ratio of source to floating gate in split-gate flash March 12, 2002
A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed ove
6277686 PIP capacitor for split-gate flash process August 21, 2001
A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, res
6242308 Method of forming poly tip to improve erasing and programming speed split gate flash June 5, 2001
A method is disclosed for forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve the erasing and programming speed of the cell. The method involves the use of an oxide other than the poly oxide that is conventionally employed in formin
6228695 Method to fabricate split-gate with self-aligned source and self-aligned floating gate to contro May 8, 2001
A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate
6214662 Forming self-align source line for memory array April 10, 2001
A method is provided for forming a source line self-aligned to adjacent transistor device. This is accomplished by a forming a self-aligned polysilicon as a source line in an opening formed in a doped polysilicon layer separated from the source line by a spacer. The alignment of the
6174772 Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate January 16, 2001
A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers s
6165845 Method to fabricate poly tip in split-gate flash December 26, 2000
A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the mini
6159801 Method to increase coupling ratio of source to floating gate in split-gate flash December 12, 2000
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6093608 Source side injection programming and tip erasing P-channel split gate flash memory cell July 25, 2000
A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a con
6067254 Method to avoid program disturb and allow shrinking the cell size in split gate flash memory May 23, 2000
A method of programming split gate flash memory cells which avoids erroneously programming non selected cells and allows the cell size and the array size to be shrunk below previously realizable limits. For N channel cells with the control gates connected to word lines and drains con










 
 
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