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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lin; Wei-Ray
Address:
Taipei, TW
No. of patents:
10
Patents:












Patent Number Title Of Patent Date Issued
6329241 Methods for producing capacitor-node contact plugs of dynamic random-access memory December 11, 2001
A method for producing capacitor-node contact plugs of a dynamic random access memory, comprising: providing a semiconductor substrate; forming at least one gate structure separated by a first isolation layer as a word line, and forming a source region and a drain region next to the word
6261923 Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local in July 17, 2001
A method for forming planarized isolation using a nitride hard mask and two CMP steps is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride and pad oxide layers are etched through where they are not covered
6255161 Method of forming a capacitor and a contact plug July 3, 2001
A method divides the formation of the contact plug connecting a source/drain region in the peripheral circuit area into two steps, wherein the capacitor can be fabricated at the same time so as to save one mask. Besides, at each step of forming the contact plug with low aspect ratio, a
6248643 Method of fabricating a self-aligned contact June 19, 2001
A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, f
6187625 Method of fabricating crown capacitor February 13, 2001
A method of fabricating a crown capacitor comprises first providing a substrate having a transistor, constituted by at least one diffused region, formed thereon and overlaid by a first insulating layer. Bit lines are formed in the first insulating layer. A first masking layer and a s
6184081 Method of fabricating a capacitor under bit line DRAM structure using contact hole liners February 6, 2001
A process for fabricating a DRAM capacitor structure, in which the capacitor upper plate structure is defined during the formation of bit line contact hole opening, and substrate contact hole opening procedure, eliminating the need for a specific upper plate, photolithographic masking
6180489 Formation of finely controlled shallow trench isolation for ULSI process January 30, 2001
A method for forming planarized shallow trench isolation is described. A nitride layer is deposited over the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the nitride layer into the semiconductor substrate wherein there are at least one wide
6159821 Methods for shallow trench isolation December 12, 2000
A method for forming self-rounded shallow trench isolation is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is then deposited overlying the pad oxide layer. Isolation trenches are then etched through the nitride and pad oxide laye
6130128 Method of fabricating crown capacitor October 10, 2000
A method of fabricating a crown capacitor comprising first providing a substrate having a transistor, constituted by at least one diffused region, formed thereon and overlaid by a first insulating layer. Bit lines are formed in the first insulating layer. A first masking layer and a
6001704 Method of fabricating a shallow trench isolation by using oxide/oxynitride layers December 14, 1999
A stacked layer including a first oxide, a nitride layer, a second oxide layer and an oxynitride layer is formed on the top of the first oxide layer. An etching is performed through a photoresist to etch the oxynitride, the second oxide and nitride. Oxide spacers are formed on the si










 
 
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