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Inventor:
Lin; Ruei-Ling
Address:
Kaohsiung, TW
No. of patents:
9
Patents:












Patent Number Title Of Patent Date Issued
6566703 High speed flash memory with high coupling ratio May 20, 2003
A flash memory device includes floating gate electrode, an interelectrode dielectric layer and a control gate electrode. The interelectrode dielectric layer is formed on top of the floating gate electrode and the control gate electrode is formed on top of the interelectrode dielectric
6281545 Multi-level, split-gate, flash memory cell August 28, 2001
A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer cov
6166410 MONOS flash memory for multi-level logic and method thereof December 26, 2000
The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage
6054348 Self-aligned source process April 25, 2000
A process for creating a semiconductor memory device, featuring the formation of FOX regions, after the creation of a source region, has been developed. The process features a source region, self-aligned to a first set of stacked gate structures, with the subsequent FOX region placed
5923974 Method of manufacture of memory device with high coupling ratio July 13, 1999
A method of forming a semiconductor memory device with a variable thickness gate oxide layer including a tunnel oxide layer and a thicker gate oxide layer includes the following steps. Provide a doped silicon semiconductor substrate coated with a tunnel oxide layer, a first floating gate
5885868 Process for fabricating SOI compact contactless flash memory cell March 23, 1999
A process for fabricating compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units is disclosed. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Float
5851881 Method of making monos flash memory for multi-level logic December 22, 1998
The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage
5851879 Method for fabricating compact contactless trenched flash memory cell December 22, 1998
A method for fabricating compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed ov
5679591 Method of making raised-bitline contactless trenched flash memory cell October 21, 1997
A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above










 
 
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