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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lin; Jyh-Rong
Address:
Tucheng, TW
No. of patents:
9
Patents:












Patent Number Title Of Patent Date Issued
8587091 Wafer-leveled chip packaging structure and method thereof November 19, 2013
A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the firs
7879438 Substrate warpage-reducing structure February 1, 2011
The subject matter disclosed herein relates to methods to reduce warpage of a substrate.
7838333 Electronic device package and method of manufacturing the same November 23, 2010
The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are
7632707 Electronic device package and method of manufacturing the same December 15, 2009
The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are
7572676 Packaging structure and method of an image sensor module August 11, 2009
This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least o
7528009 Wafer-leveled chip packaging structure and method thereof May 5, 2009
This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating la
7411306 Packaging structure and method of an image sensor module August 12, 2008
This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least o
7294920 Wafer-leveled chip packaging structure and method thereof November 13, 2007
This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating la
6605525 Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and August 12, 2003
A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks as stress buffering layer and package formed are described. The method incorporates the step of forming metal lines in-between the plurality of IC dies on a wafer during the same process use










 
 
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