| Patent Number |
Title Of Patent |
Date Issued |
| 7553772 |
Process and apparatus for simultaneous light and radical surface treatment of integrated circuit |
June 30, 2009 |
| Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with |
| 7405116 |
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow |
July 29, 2008 |
| A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals use |
| 7365015 |
Damascene replacement metal gate process with controlled gate profile and length using Si.sub.1- |
April 29, 2008 |
| A method of forming a metal gate in a wafer. PolySi.sub.1-xGe.sub.x and polysilicon are used to form a tapered groove. Gate oxide, PolySi.sub.1-xGe.sub.x, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi.sub.1-xGe.sub.x, and ga |
| 7341978 |
Superconductor wires for back end interconnects |
March 11, 2008 |
| An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the elect |
| 7259462 |
Interconnect dielectric tuning |
August 21, 2007 |
| An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the |
| 7189628 |
Fabrication of trenches with multiple depths on the same substrate |
March 13, 2007 |
| Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow |
| 7081406 |
Interconnect dielectric tuning |
July 25, 2006 |
| An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the |
| 6864152 |
Fabrication of trenches with multiple depths on the same substrate |
March 8, 2005 |
| Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow tren |
| 6818516 |
Selective high k dielectrics removal |
November 16, 2004 |
| A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, ther |
| 6806038 |
Plasma passivation |
October 19, 2004 |
| A method for forming a conductive trace on a substrate. The conductive trace is patterned with a photoresist mask and etched, thereby forming a polymer layer on a top surface and sidewalls of the photoresist mask and on sidewalls of the conductive trace. The polymer layer contains entrai |
| 6794304 |
Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene |
September 21, 2004 |
| A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially |
| 6746925 |
High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidation |
June 8, 2004 |
| In a method of forming an integrated circuit device, sidewall oxides are formed by plasma oxidation on the patterned gate. This controls encroachment beneath a dielectric layer underlying the patterned gate. The patterned gate is oxidized using in-situ O.sub.2 plasma oxidation. The p |
| 6743669 |
Method of reducing leakage using Si3N4 or SiON block dielectric films |
June 1, 2004 |
| A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si.sub.3 N.sub.4 is disposed on the oxide |
