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Inventor:
Lin; Derrick Chu
Address:
Foster City, CA
No. of patents:
14
Patents:












Patent Number Title Of Patent Date Issued
7480686 Method and apparatus for executing packed shift operations January 20, 2009
A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation and whether the shift
7461109 Method and apparatus for providing packed shift operations in a processor December 2, 2008
A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register
7451169 Method and apparatus for providing packed shift operations in a processor November 11, 2008
A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that
7117232 Method and apparatus for providing packed shift operations in a processor October 3, 2006
A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that
6901420 Method and apparatus for performing packed shift operations May 31, 2005
A method and apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted
6738793 Processor capable of executing packed shift operations May 18, 2004
An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed
6631389 Apparatus for performing packed shift operations October 7, 2003
An apparatus for performing a shift operation on a packed data element having a multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed
6275834 Apparatus for performing packed shift operations August 14, 2001
An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed
6035316 Apparatus for performing multiply-add operations on packed data March 7, 2000
A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first
5991884 Method for reducing peak power in dispatching instructions to multiple execution units November 23, 1999
A method of reducing microprocessor peak power by scheduling execution of instructions to multiple execution units. In the prior art, parallel processing of instructions by high-power execution units caused the microprocessor peak power to increase. The method of the present invention
5974525 System for allowing multiple instructions to use the same logical registers by remapping them to October 26, 1999
A technique for increasing the number of physical segment registers by renaming logical segment registers into a larger register space. The remapping of the segment registers allows for instructions accessing the segment registers to be executed non-serially. The renaming of segment
5959874 Method and apparatus for inserting control digits into packed data to perform packed arithmetic September 28, 1999
A processor having a circuit for performing a packed addition and/or packed subtraction operation. The decoder accesses the registers addressed by SRC1 and SRC2. These registers provide a first packed data and a second packed data to the circuit. Packed data consists of a number of fixed
5881279 Method and apparatus for handling invalid opcode faults via execution of an event-signaling micr March 9, 1999
A microprocessor that handles invalid opcodes via an event-signaling micro-operation is disclosed. The microprocessor comprises a decoder that decodes macroinstructions, including an opcode, into a single microprocessor cycle micro-operation. The decoder detects invalid opcodes and r
5835782 Packed/add and packed subtract operations November 10, 1998
A processor having a circuit for performing a packed addition and/or packed subtraction operation. The decoder accesses the registers addressed by SRC1 and SRC2. These registers provide a first packed data and a second packed data to the circuit. Packed data consists of a number of fixed










 
 
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