| Patent Number |
Title Of Patent |
Date Issued |
| 7626853 |
Method of operating memory cell providing internal power switching |
December 1, 2009 |
| Various implementations are provided that may be used to improve the writeability of individual memory cells providing internal power switching. For example, in one implementation, a method is provided for operating a memory device including a first static random access memory (SRAM) |
| 7567124 |
Symmetrical differential amplifier |
July 28, 2009 |
| A differential amplifier has improved power efficiency, reduced offset penalty and a symmetrical output differential signal. Such a differential amplifier may include: (a) a bias circuit that has a first input device and a second input device; (b) a first load device and a second load |
| 7512695 |
Method and system to control the communication of data between a plurality of interconnect devic |
March 31, 2009 |
| A method and system of communicating data between a source interconnect device and a destination interconnect device are defined. The method includes adding an identification component to the data at the source interconnect device prior to communicating the data, and extracting the i |
| 7256621 |
Keeper circuits having dynamic leakage compensation |
August 14, 2007 |
| Disclosed are keeper circuits for electronic circuits that selectively maintain the voltage level of an intermediate circuit node at a desired level. In one exemplary embodiment, a keeper transistor either provides current or drains current from the intermediate node to maintain the |
| 7054330 |
Mask-based round robin arbitration |
May 30, 2006 |
| A method and system to arbitrate between a plurality of resource requests are disclosed. In each arbitration within a current round of arbitration, a winning request is identified based on a priority associated with each requester participating in the arbitration and a set of values stor |
| 6763418 |
Request bus arbitration |
July 13, 2004 |
| A method and system to arbitrate requests of a plurality of ports of an interconnect device are provided. Every port receives combined pending request data that includes a pending request indicator associated with each of the plurality of ports. Each pending request indicator specifies |
| 5893931 |
Lookaside buffer for address translation in a computer system |
April 13, 1999 |
| A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a |
| 5680566 |
Lookaside buffer for inputting multiple address translations in a computer system |
October 21, 1997 |
| A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a |
