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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lien; Chuen-Der
Address:
Mountain View, CA
No. of patents:
28
Patents:












Patent Number Title Of Patent Date Issued
6372641 Method of forming self-aligned via structure April 16, 2002
A self-aligned via between interconnect layers in an integrated circuit, and a process for forming such a via which allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density.
6278162 ESD protection for LDD devices August 21, 2001
A semiconductor integrated circuit suitable for use in an ESD protection circuit is disclosed. A substrate has an active region formed therein so as to define a P/N junction therebetween. An insulating region is formed near the surface of the substrate adjacent the active region thus def
5846868 Method for forming a walled-emitter transistor December 8, 1998
An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are
5834125 Non-reactive anti-reflection coating November 10, 1998
An anti-reflection coating is provided that has a barrier layer and an anti-reflective layer. The barrier layer stops reactions between the anti-reflective layer and underlying layers or substrates, does not make the anti-reflective layer reflective, and preferably does not react with
5820926 Process for forming and using a non-reactive anti-reflection coating October 13, 1998
An anti-reflection coating is provided that has a barrier layer and an anti-reflective layer. The barrier layer stops reactions between the anti-reflective layer and underlying layers or substrates, does not make the anti-reflective layer reflective, and preferably does not react with
5786245 Method for forming a stable SRAM cell using low backgate biased threshold voltage select transis July 28, 1998
A more stable SRAM cell is provided by reducing the backgate biased threshold voltage of the SRAM's select transistor. In some embodiments, masking layers are used during dopant implantation of the select transistors to minimize the net dopant concentration in the select transistor's
5681769 Method of fabricating a high capacitance insulated-gate field effect transistor October 28, 1997
A high capacitance field effect transistor for use in an integrated memory circuit is fabricated with an optimized gate electrode and active region overlap, increasing the gate electrode to substrate capacitance thereby minimizing the effect of alpha particle upset. The optimized overlap
5652456 Semiconductor structure containing multiple optimized well regions July 29, 1997
A BiCMOS process is provided for fabricating on the same semiconductor substrate three types of N-wells optimized respectively for (i) PMOS FETs requiring low P+/N-well capacitance; (ii) NPN bipolar transistors which do not require low collector-to-substrate capacitance and PMOS FETs whi
5644155 Structure and fabrication of high capacitance insulated-gate field effect transistor July 1, 1997
A high capacitance field effect transistor for use in an integrated memory circuit is fabricated with an optimized gate electrode and active region overlap, increasing the gate electrode to substrate capacitance thereby minimizing the effect of alpha particle upset. The optimized overlap
5574305 Walled-emitter transistor November 12, 1996
An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are
5572460 Static random-access memory cell with capacitive coupling to reduce sensitivity to radiation November 5, 1996
Radiation hardening for a static memory cell that centers around a pair of storage transistors (QS1 and QS2) coupled to a load (30) for storing a bit of information is achieved with a coupling capacitor (CC) situated between the storage transistors. In an MOS implementation, the coupling
5514613 Parallel manufacturing of semiconductor devices and the resulting structure May 7, 1996
In accordance with this invention, integrated circuits are manufactured using parallel processing to manufacture separately selected parts of finished integrated circuits. Upon completion of the parts, the parts are joined together to form the completed integrated circuit. For example, a
5510744 Control circuit for reducing ground and power bounce from an output driver circuit April 23, 1996
A control circuit for controlling the power or bounce of an output driver circuit is disclosed. The control circuit can sense the output voltage and/or the bounce and then adjust the control node voltage of the output driver circuit accordingly. In addition, the output circuit can discha
5479039 MOS electrostatic discharge protection device and structure December 26, 1995
A PMOS transistor is coupled directly to both V.sub.CC and V.sub.SS, for use in an electrostatic discharge (ESD) protection device, thereby protecting the I/O pad(s) of an integrated circuit. The direct coupling of the PMOS transistor to both voltage levels, V.sub.CC and V.sub.SS, greatl
5471094 Self-aligned via structure November 28, 1995
A self-aligned via between interconnect layers in an integrated circuit allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density and improved yield. In one embodiment, self-aligned vias are used to connect first and second i
5470766 Efficient method for fabricating optimal BiCMOS N-wells for bipolar and field effect transistors November 28, 1995
A BiCMOS process is provided for fabricating on the same semiconductor substrate three types of N-wells optimized respectively for (i) PMOS FETs requiring low P+/N-well capacitance; (ii) NPN bipolar transistors which do not require low collector-to-substrate capacitance and PMOS FETs whi
5401997 ESD protection for poly resistor on oxide March 28, 1995
An improved Electrostatic Discharge (ESD) protection device for use in the electrostatic discharge testing of an integrated circuit (IC). In accordance with the invention, a p-n junction is formed beneath a polysilicon resistor, with a metal oxide layer separating the resistor and th
5393677 Method of optimizing wells for PMOS and bipolar to yield an improved BICMOS process February 28, 1995
A first process embodiment of the present invention comprises the steps of implanting a blanket low dose n-well implant before field oxidation. A blanket n-type punchthrough suppression implant precedes the field oxidation step. After field oxidation, an implantation masking step is
5310700 Conductor capacitance reduction in integrated circuits May 10, 1994
A passive semiconductor structure for reduction of the mutual capacitance between parallel conductors, with two parallel conductors separated from a substrate by a first dielectric layer and covered by a second dielectric layer. The second dielectric layer having a cavity formed between
5284800 Method for preventing the exposure of borophosphosilicate glass to the ambient and stopping phos February 8, 1994
An embodiment of the present invention is a semiconductor fabrication process that deposits an oxide layer after a step to make contact openings in a BPSG layer and before a contact reflow step. The oxide allows implant dopants to be properly activated in the contact reflow step without
5258317 Method for using a field implant mask to correct low doping levels at the outside edges of the b November 2, 1993
An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are
5250854 Bitline pull-up circuit operable in a low-resistance test mode October 5, 1993
A method and apparatus for raising bitlines selectively to desired voltage levels. The circuit of the invention can be controlled to operate either in a first mode (for raising the bitlines selectively to relatively low voltage levels) or in a second mode (for raising the bitlines to des
5182475 ECL to CMOS voltage translator with bipolar transistor January 26, 1993
An improved circuit for translating ECL level voltages to CMOS level voltages. The circuit of the invention has a voltage gain stage with a bipolar transistor connected to a PMOS transistor, and a resistive loading stage including NMOS transistors. The bipolar transistor functions to
5173627 Circuit for outputting a data signal following an output enable command signal December 22, 1992
The invention provides an output enable control circuit with a three gate delay. The circuit includes a CMOS passgate or other transmission control and filtering means, one or more shunting transistors, and an output driver. The CMOS passgate, in conjunction with a first shunting tra
5128731 Static random access memory cell using a P/N-MOS transistors July 7, 1992
A P/N-MOS transistor having source and drain of opposite semiconductor types is provided. One embodiment of the P/N-MOS transistor has turn-off characteristic similar to a PMOS transistor, and turn-on characteristic similar to a PMOS transistor connected in series with a p-n junction
5079447 BiCMOS gates with improved driver stages January 7, 1992
In accordance with the present invention, an improved output driver stage for a BiCMOS logic gate is provided by including a clamping transistor. Such clamping transistor avoids, in the pull-up bipolar transistor, both degradation of current gain and emitter-to-collector breakdown.
5008568 CMOS output driver April 16, 1991
A transistor configured as a capacitor is connected between the gate and drain of an output, pull-down transistor to limit the rate of change (di/dt) of the current conducted through the pull-down transistor during the turn-on of the transistor to limit ground bounce (transients). Drive
4933574 BiCMOS output driver June 12, 1990
A bipolar transistor and two field-effect transistors are connected in a BiCMOS pull-down configuration to pull-down to a (first) predetermined potential level the potential developed on an output line when a high logic level potential is developed on an input line. To maximize switching










 
 
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