| Patent Number |
Title Of Patent |
Date Issued |
| 6738305 |
Standby mode circuit design for SRAM standby power reduction |
May 18, 2004 |
| This invention provides a new standby mode circuit design which reduces the power dissipation of static random access memory, SRAM circuitry. The circuit and method of this invention provides a reduced power supply voltage to SRAM memory cells so as to reduce the power dissipation of |
| 6614067 |
Design and process for a dual gate structure |
September 2, 2003 |
| A process for fabricating a polysilicon dual gate structure, featuring the use of a tungsten plug structure, used to alleviate the diode effect, present at the dopant interface in the polysilicon dual gate structure, has been developed. A first iteration of this invention places the |
| 6597055 |
Redundancy structure in self-aligned contacts |
July 22, 2003 |
| A fuse link redundancy structure to implement redundant circuits within an integrated circuit has an insulating layer over a conductive layer of the fuse link is sufficiently thin and transparent to allow destruction of the conductive layer by an intense laser light. The redundancy struc |
| 6569723 |
Crossed strapped VSS layout for full CMOS SRAM cell |
May 27, 2003 |
| This method forms an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device. First form an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transis |
| 6448140 |
Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure i |
September 10, 2002 |
| A process for fabricating composite insulator spacers, comprised of an underlying silicon oxide sidewall layer, and an overlying silicon nitride layer, formed on the sides of a polycide gate structure, has been developed. The process features initially, laterally recessing the exposed |
| 6417032 |
Method of forming cross strapped Vss layout for full CMOS SRAM cell |
July 9, 2002 |
| This method forms an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device. First form an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transis |
| 6413803 |
Design and process for a dual gate structure |
July 2, 2002 |
| A process for fabricating a polysilicon dual gate structure, featuring the use of a tungsten plug structure, used to alleviate the diode effect, present at the dopant interface in the polysilicon dual gate structure, has been developed. A first iteration of this invention places the |
| 6380024 |
Method of fabricating an SRAM cell featuring dual silicide gates and four buried contact regions |
April 30, 2002 |
| A process of fabricating an SRAM cell, comprised with four NMOS devices, and two PMOS devices, featuring a dual gate polycide structure, traversing both NMOS and PMOS device regions, and featuring buried contact regions used for connection of specific NMOS drain regions, and used for |
| 6319758 |
Redundancy structure in self-aligned contact process |
November 20, 2001 |
| A fuse link redundancy structure to implement redundant circuits within an integrated circuit has an insulating layer over a conductive layer of the fuse link is sufficiently thin and transparent to allow destruction of the conductive layer by an intense laser light. The redundancy struc |
| 6271570 |
Trench-free buried contact |
August 7, 2001 |
| A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. |
| 6265295 |
Method of preventing tilting over |
July 24, 2001 |
| A new method is provided for the creation of metal plugs. After the gate electrode structures have been created on the surface of a semiconductor substrate, the Inter Level Dielectric (ILD) is deposited over the poly gates. The layer of ILD is polished, a second layer of dielectric is |
| 6258678 |
Use of a wet etch dip step used as part of a self-aligned contact opening procedure |
July 10, 2001 |
| A process for forming a SAC opening, in a composite insulator layer, to expose an active device region in a semiconductor substrate, has been developed. The process features a RIE procedure, used to selectively define a first portion of the SAC opening, in a thick silicon oxide layer, |
| 6255715 |
Fuse window guard ring structure for nitride capped self aligned contact processes |
July 3, 2001 |
| The present invention provides a structure and method for forming a moisture barrier guard ring structure 38 44 48 52 54 for around a fuse window 30 in a semiconductor device. The invention begins by forming a fuse structure 32 33 34 over the isolation regions cross the fuse window a |
| 6239458 |
Polysilicon-via structure for four transistor, triple polysilicon layer SRAM cell including two |
May 29, 2001 |
| This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to the well. Form an intermediate |
| 6228731 |
Re-etched spacer process for a self-aligned structure |
May 8, 2001 |
| A process for forming a self-aligned contact, (SAC), structure, on an active device region in a semiconductor substrate, exposed at the bottom of a SAC opening in an insulator layer, has been developed. The process features increasing the area of the active device region, used to acc |
| 6228726 |
Method to suppress CMOS device latchup and improve interwell isolation |
May 8, 2001 |
| A method for processing a semiconductor device with improved latchup immunity and interwell isolation is described. Shallow trench isolation areas are formed on a semiconductor substrate to provide electrical isolation for active device N and P well areas. The active areas will conta |
| 6214698 |
Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer |
April 10, 2001 |
| A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and side walls of the trench. An undo |
| 6214656 |
Partial silicide gate in sac (self-aligned contact) process |
April 10, 2001 |
| A method for integrating salicide and self-aligned contact processes in the fabrication integrated circuits is described. A polysilicon layer is deposited overlying a gate oxide layer and isolation areas. Ions are implanted into the polysilicon layer to define a surface channel dual gate |
| 6180530 |
Self-aligned contact structure |
January 30, 2001 |
| A method for forming a SAC structure, for a SRAM device, has been developed. The SAC structure is comprised of a narrow portion, located in a narrow region of the SAC opening, contacting an active device region, in narrow spaces between polysilicon gate structures. The SAC structure is |
| 6177338 |
Two step barrier process |
January 23, 2001 |
| A process for forming a tungsten plug structure, in a narrow diameter contact hole, has been developed. The process features the use of a composite layer, comprised on an underlying titanium layer, and an overlying, first titanium nitride barrier layer, on the walls, and at the botto |
| 6174775 |
Method for making a dual gate structure for CMOS device |
January 16, 2001 |
| A process for fabricating a polycide, dual gate structure, for CMOS devices, featuring an undoped polysilicon layer, located between an overlying metal silicide layer, and an underlying dual doped polysilicon layer, has been developed. A first undoped polysilicon layer is converted t |
| 6121684 |
Integrated butt contact having a protective spacer |
September 19, 2000 |
| The present invention provides a structure and method of forming a butting contact having protective spacers 50A that prevent shorting between a second polysilicon layer 60 and the substrate in a hole 20A in a isolation region 20. The following are provide: a isolation region 20, a first |
| 6090674 |
Method of forming a hole in the sub quarter micron range |
July 18, 2000 |
| Improved etching of sub-micron diameter via or contact holes in integrated circuits is achieved by first coating the dielectric layer through which the hole is to be etched with successive layers of titanium and silicon oxynitride. This is followed by coating with a conventional photores |
| 6080647 |
Process to form a trench-free buried contact |
June 27, 2000 |
| A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. |
| 6071798 |
Method for fabricating buried contacts |
June 6, 2000 |
| The present invention provides a novel method for fabricating a buried contact extending under the first conductive layer 16 and subjacent first insulating layer 14. A first insulating layer 14 and a first conductive layer are formed over a silicon substrate 10 having isolation structure |
| 6063711 |
High selectivity etching stop layer for damascene process |
May 16, 2000 |
| A high selectivity etch-stop layer comprising oxynitride is disclosed for forming damascene structures in the manufacturing of semiconductor substrates. Because of its relatively high selectivity to oxides, the oxynitride etch-stop can be made thinner than the conventionally used nit |
| 6020267 |
Method for forming local interconnect metal structures via the addition of a titanium nitride an |
February 1, 2000 |
| A method for fabricating local interconnect metal structures, overlying metal filled via hole openings, has been developed. This invention features the creation of an aluminum based interconnect structure, comprised with an underlying titanium nitride layer. The titanium nitride laye |
| 6013547 |
Process for creating a butt contact opening for a self-aligned contact structure |
January 11, 2000 |
| A method for fabricating a memory device, using a butt contact opening, and an overlying SAC structure, to allow connection between a gate structure, and an active device region, in a semiconductor substrate, has been developed. This invention features the use of an organic layer, protec |
| 5998249 |
Static random access memory design and fabrication process featuring dual self-aligned contact s |
December 7, 1999 |
| A method for forming an SRAM cell, on a semiconductor substrate, comprised of MOSFET devices, and polysilicon load resistors, has been developed. The process for forming the SRAM cell features the use of two, self-aligned contact, (SAC), structures, a polycide SAC structure, used for con |
| 5986328 |
Buried contact architecture |
November 16, 1999 |
| An method for the fabrication of an improved polysilicon buried contact is described. The contact is formed within a trench etched into the silicon substrate. The effective area of the contact is thereby increased over the conventional planar buried contact by an amount equal to the area |
| 5972759 |
Method of making an integrated butt contact having a protective spacer |
October 26, 1999 |
| The present invention provides a structure and method of forming a butting contact having protective spacers 50A that prevent shorting between a second polysilicon layer 60 and the substrate in a hole 20A in a isolation region 20. The following are provide: a isolation region 20, a first |
| 5970346 |
Fuse window guard ring structure for nitride capped self aligned contact processes |
October 19, 1999 |
| The present invention provides a structure and method for forming a moisture barrier guard ring structure 38 44 48 52 54 for around a fuse window 30 in a semiconductor device. The invention begins by forming a fuse structure 32 33 34 over the isolation regions cross the fuse window a |
| 5960276 |
Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench i |
September 28, 1999 |
| A method to form, in a NMOS area, a shallow trench isolation (STI) having B doped sidewalls regions 44 to reduce the NMOS reverse narrow width effect in narrow active areas 12N (e.g., narrow channel regions <0.1 .mu.m wide). A substrate is provided having a NMOS area 13 and a PMOS are |
| 5955768 |
Integrated self-aligned butt contact process flow and structure for six transistor full compleme |
September 21, 1999 |
| A method of forming a contact between a conductor and a substrate region in a MOSFET device is provided starting with forming a semiconductor substrate with a silicon oxide layer formed on the surface thereof. Then form a stack of a conductor material upon the surface of the silicon oxid |
| 5930633 |
Integrated butt-contact process in shallow trench isolation |
July 27, 1999 |
| A new method of forming a butted contact in combination with a shallow trench isolation process is described. Shallow trench isolation areas are formed within the semiconductor substrate and filled with an oxide. A first photomask is formed having an opening larger than the butted contac |
| 5926728 |
Method for fabricating tungsten polycide contacts |
July 20, 1999 |
| A method for fabricating polycide contacts to semiconductor substrates, and more specifically for self-aligned contacts on substrates having field effect transistors (FETs) is achieved. After forming conventional FETs from a patterned first polysilicon layer provided with contact areas, |
| 5926706 |
Method for making a trench-free buried contact with low resistance on semiconductor integrated c |
July 20, 1999 |
| A method is achieved for forming buried contacts with diffused contact regions on semiconductor integrated circuits having low sheet resistance between the buried contacts and the field effect transistors. The method also allows for greater misalignment tolerances that prevent trenching |
| 5920098 |
Tungsten local interconnect, using a silicon nitride capped self-aligned contact process |
July 6, 1999 |
| MOSFET devices, using a local interconnect structure, and silicon nitride capped, self-aligned contact openings, have been developed. The process features the creation of self-aligned contact openings, exposing specific source and drain regions. After deposition of a composite insulator |
| 5904531 |
Method of increasing the area of a buried contact region |
May 18, 1999 |
| A process for forming an increased surface area, buried contact region, for a MOSFET device, has been developed. The process features creating a mini-trench, in an insulator filled shallow trench, exposing a vertical surface of the semiconductor substrate, along the side of the mini-tren |
| 5872063 |
Self-aligned contact structures using high selectivity etching |
February 16, 1999 |
| A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and si |
| 5866449 |
Method of making polysilicon-via structure for four transistor, triple polysilicon layer SRAM ce |
February 2, 1999 |
| This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to the well. Form an intermediate |
| 5851912 |
Modified tungsten-plug contact process |
December 22, 1998 |
| An method for the fabrication of an ohmic, low resistance contact to heavily doped silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for surface planarization using a borophosphosilicate glass insulator deposited on the |
| 5843816 |
Integrated self-aligned butt contact process flow and structure for six transistor full compleme |
December 1, 1998 |
| A method of forming a contact between a conductor and a substrate region in a MOSFET device is provided starting with forming a semiconductor substrate with a silicon oxide layer formed on the surface thereof. Then form a stack of a conductor material upon the surface of the silicon oxid |
| 5827764 |
Method for reducing the contact resistance of a butt contact |
October 27, 1998 |
| The present invention provides a method of forming a low contact resistance butt contact 44 between a doped region 30 and a conductive line 16B 18B. The method begins by providing an isolation region 11 on a substrate. A conductive structure 16B 18B comprised of a first polysilicon line |
| 5807779 |
Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact |
September 15, 1998 |
| A process for fabricating MOSFET devices, using a local interconnect structure, and silicon nitride capped, self-aligned contact openings, has been developed. The process features the creation of self-aligned contact openings, exposing specific source and drain regions. After deposition |
| 5795827 |
Method for reducing the resistance of self-aligned contacts, for triple polysilicon SRAM devices |
August 18, 1998 |
| A process for fabricating MOSFET devices, for a SRAM cell, using a polycide contact structure, self-aligned to an underlying source and drain region, has been developed. This process features the use of a high temperature, rapid thermal anneal step, used to dissolve native oxide at the |
| 5780331 |
Method of making buried contact structure for a MOSFET device in an SRAM cell |
July 14, 1998 |
| A process for creating a buried contact structure, for a MOSFET device, to be used in an SRAM cell, has been developed. The process features using a thick tungsten silicide layer, on the sides of a split polysilicon shape, followed by a series of selective, anisotropic RIE procedures, us |
| 5763303 |
Rapid thermal chemical vapor deposition procedure for a self aligned, polycide contact structure |
June 9, 1998 |
| A process for fabricating MOSFET devices, for a SRAM cell, using a polycide contact structure, self-aligned to an underlying source and drain region, has been developed. This process features the use of a RTCVD procedure, featuring loading of wafers, as well as evacuation procedures, bot |
| 5721146 |
Method of forming buried contact architecture within a trench |
February 24, 1998 |
| An method for the fabrication of an improved polysilicon buried contact is described. The contact is formed within a trench etched into the silicon substrate. The effective area of the contact is thereby increased over the conventional planar buried contact by an amount equal to the area |
| 5705436 |
Method for forming a poly load resistor |
January 6, 1998 |
| A physical implementation and method for achieving it are described for a load resistor and bus line subcircuit such as might be used in an SRAM cell. This was achieved by using two layers of polysilicon. The first polysilicon layer has low resistivity and serves to make effective contac |
