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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Liaw; Corvin
Address:
Munchen, DE
No. of patents:
8
Patents:












Patent Number Title Of Patent Date Issued
7561460 Resistive memory arrangement July 14, 2009
Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM
7402490 Charge-trapping memory device and methods for operating and manufacturing the cell July 22, 2008
To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts
7280392 Integrated memory device and method for operating the same October 9, 2007
A memory device includes an array of memory cells that include a memory element having a non-reactive resistance whose magnitude is programmable to assume a high-resistance state or a low-resistance state. Sets of first and second lines provide access to the memory cells, wherein the
7272040 Multi-bit virtual-ground NAND memory device September 18, 2007
An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a b
7254052 Memory circuit and method for reading out a memory datum from such a memory circuit August 7, 2007
The present invention relates to a memory circuit comprising a CBRAM resistance memory cell, which is connected to a bit line and a word line and has a CBRAM resistance element, the resistance of which can be set by means of a write current, in order to store an item of information, and
7250651 Semiconductor memory device comprising memory cells with floating gate electrode and method of p July 31, 2007
Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the
7215568 Resistive memory arrangement May 8, 2007
Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM
7049651 Charge-trapping memory device including high permittivity strips May 23, 2006
The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is perform










 
 
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