| Patent Number |
Title Of Patent |
Date Issued |
| 7526631 |
Data processing system with backplane and processor books configurable to support both technical |
April 28, 2009 |
| A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with extern |
| 7308558 |
Multiprocessor data processing system having scalable data interconnect and data routing mechani |
December 11, 2007 |
| The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a dat |
| 7302616 |
Method and apparatus for performing bus tracing with scalable bandwidth in a data processing sys |
November 27, 2007 |
| An apparatus for performing bus tracing with scalable bandwidth in a distributed memory symmetric multiprocesssor system is disclosed. The distributed memory symmetric multiprocessor system includes multiple processing units, each coupled to a memory module. Each of the processing un |
| 7213169 |
Method and apparatus for performing imprecise bus tracing in a data processing system having a d |
May 1, 2007 |
| An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and |
| 7007128 |
Multiprocessor data processing system having a data routing mechanism regulated through control |
February 28, 2006 |
| A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a da |
| 6910062 |
Method and apparatus for transmitting packets within a symmetric multiprocessor system |
June 21, 2005 |
| The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated fo |
| 6865695 |
Robust system bus recovery |
March 8, 2005 |
| A computer system of a number of processing nodes operate either in a loop configuration or off of a common bus with high speed, high performance wide bandwidth characteristics. The processing nodes in the system are also interconnected by a separate narrow bandwidth, low frequency recov |
| 6848003 |
Multi-node data processing system and communication protocol that route write data utilizing a d |
January 25, 2005 |
| A data processing system includes a plurality of nodes, which each contain at least one agent and each have an associated node identifier, and memory distributed among the plurality of nodes. The data processing system further includes an interconnect containing a segmented data channel, |
| 6823471 |
Method for providing high availability within a data processing system via a reconfigurable hash |
November 23, 2004 |
| A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, a |
| 6801984 |
Imprecise snooping based invalidation mechanism |
October 5, 2004 |
| A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided a set of directional bits in addition to the coherency state bits and the address tag. The |
| 6701416 |
Cache coherency protocol with tagged intervention of modified values |
March 2, 2004 |
| A cache coherency protocol uses a "Tagged" coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migra |
| 6671712 |
Multi-node data processing system having a non-hierarchical interconnect architecture |
December 30, 2003 |
| A data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The plurality of nodes are coupled by a non-hierarchical interconnect including multiple non-blocking uni-directional address channel |
| 6662216 |
Fixed bus tags for SMP buses |
December 9, 2003 |
| According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respe |
| 6658556 |
Hashing a target address for a memory access instruction in order to determine prior to executio |
December 2, 2003 |
| A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store un |
| 6658536 |
Cache-coherency protocol with recently read state for extending cache horizontally |
December 2, 2003 |
| A method of extending a cache of a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. A value is loaded from system memory into one or |
| 6598118 |
Data processing system with HSA (hashed storage architecture) |
July 22, 2003 |
| A processor having a hashed and partitioned storage subsystem includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a cache subsystem including a plurality of caches that store data utilized by the execution unit. Each cache among the plu |
| 6591321 |
Multiprocessor system bus protocol with group addresses, responses, and priorities |
July 8, 2003 |
| A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are snooping on. at least one bus line. Snoop response groups which are groups of different types of |
| 6591307 |
Multi-node data processing system and method of queue management in which a queued operation is |
July 8, 2003 |
| A data processing system includes an interconnect, a plurality of nodes coupled to the interconnect that each include at least one agent, response logic within each node, and a queue. In response to snooping a transaction on the interconnect, each agent outputs a snoop response. In addit |
| 6587926 |
Incremental tag build for hierarchical memory architecture |
July 1, 2003 |
| A method and system for managing a data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device to multiple data storage devices within the hierarchical data storage |
| 6587925 |
Elimination of vertical bus queueing within a hierarchical memory architecture |
July 1, 2003 |
| A method and system for processing a split data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device onto an address bus that is shared by a plurality of data storage |
| 6587924 |
Scarfing within a hierarchical memory architecture |
July 1, 2003 |
| A method and system for scarfing data during a data access transaction within a hierarchical data storage system. A data access request is delivered from a source device to a plurality of data storage devices. The access request includes a target address and a source path tag, wherein |
| 6553447 |
Data processing system with fully interconnected system architecture (FISA) |
April 22, 2003 |
| A Fully Interconnected System Architecture (FISA) for an improved data processing system. The data processing system topology has a processor chip and external components to the processor chip, such as memory and input/output (I/O) and other processor chips. The processor chip is int |
| 6553442 |
Bus master for SMP execution of global operations utilizing a single token with implied release |
April 22, 2003 |
| In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits a token required to complete the global operation and iden |
| 6519665 |
Multi-node data processing system and communication protocol in which a stomp signal is propagat |
February 11, 2003 |
| A data processing system includes at least first and second nodes and a segmented interconnect having coupled first and second segments. The first node includes the first segment and first and second agents coupled to the first segment, and the second node includes the second segment and |
| 6519649 |
Multi-node data processing system and communication protocol having a partial combined response |
February 11, 2003 |
| A data processing system includes an interconnect and first and second nodes, coupled to the interconnect, that each include at least one agent. Each agent within the first and second nodes outputs a snoop response in response to snooping a transaction on the interconnect. Utilizing the |
| 6516404 |
Data processing system having hashed architected processor facilities |
February 4, 2003 |
| A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of gro |
| 6516368 |
Bus master and bus snooper for execution of global operations utilizing a single token for multi |
February 4, 2003 |
| In response to a need to initiate one or more global operations, a bus master within a multiprocessor system issues a combined token and operation request in a single bus transaction on a bus coupled to the bus master. The combined token and operation request solicits a single existi |
| 6507880 |
Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple t |
January 14, 2003 |
| In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits one of a plurality of tokens required to complete the glob |
| 6505277 |
Method for just-in-time delivery of load data by intervening caches |
January 7, 2003 |
| A method for ordering the time of issue of a load instruction from a lower level (L2) intervening cache, interlinked by a system bus to a first L2 cache. The method comprises the steps of (i) appending a cycle of dependency (CoD) value to said load instruction, where the CoD value co |
| 6502171 |
Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf d |
December 31, 2002 |
| In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs a horizontal storage device at the same level as the storage device initiating the combined operation to allocate and store either th |
| 6502168 |
Cache having virtual cache controller queues |
December 31, 2002 |
| According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation |
| 6480975 |
ECC mechanism for set associative cache array |
November 12, 2002 |
| A method of checking for errors in a set associative cache array, by comparing a requested value to values loaded in the cache blocks and determining, concurrently with this comparison, whether the cache blocks collectively contain at least one error (such as a soft error caused by s |
| 6480915 |
Bus protocol and token manager for SMP execution of global operations utilizing a single token w |
November 12, 2002 |
| Serialization of global operations within a multiprocessor system is achieved utilizing a single token, requiring a bus master to acquire the token for completion of each individual global operation initiated by that bus master. A combined token and operation request, in which a token |
| 6477613 |
Cache index based system address bus |
November 5, 2002 |
| Following a cache miss by an operation, the address for the operation is transmitted on the bus coupling the cache to lower levels of the storage hierarchy. A portion of the address including the index field is transmitted during a first bus cycle, and may be employed to begin direct |
| 6470442 |
Processor assigning data to hardware partition based on selectable hash of data address |
October 22, 2002 |
| A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, a |
| 6460101 |
Token manager for execution of global operations utilizing multiple tokens |
October 1, 2002 |
| Serialization of global operations within a multi-processor system is achieved utilizing a plurality of tokens each permitting completion of a single global operation, requiring a bus master to acquire the token for completion of each individual global operation initiated by that bus |
| 6460100 |
Bus snooper for SMP execution of global operations utilizing a single token with implied release |
October 1, 2002 |
| Only a single snooper queue for global operations within a multiprocessor system is implemented within each bus snooper, controlled by a single token allowing completion of one operation. A bus snooper, upon detecting a combined token and operation request, begins speculatively processin |
| 6449691 |
Asymmetrical cache properties within a hashed storage subsystem |
September 10, 2002 |
| A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, have diverse cache hardware and each preferably store only data having |
| 6446165 |
Address dependent caching behavior within a data processing system having HSA (hashed storage ar |
September 3, 2002 |
| A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one |
| 6442629 |
Bus protocol and token manager for execution of global operations utilizing a single token with |
August 27, 2002 |
| Serialization of global operations within a multiprocessor system is achieved utilizing a single token, requiring a bus master to acquire the token for completion of one or more global operations to be initiated by that bus master. A combined token and operation request, in which a token |
| 6430683 |
Processor and method for just-in-time delivery of load data via time dependency field |
August 6, 2002 |
| A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. Th |
| 6427204 |
Method for just in-time delivery of instructions in a data processing system |
July 30, 2002 |
| A system for time-ordered issuance of instruction fetch requests (IFR). More specifically, the system enables just-in-time delivery of instructions requested by an IFR. The system consists of a processor, an L1 instruction cache with corresponding L1 cache controller, and an instruct |
| 6425090 |
Method for just-in-time delivery of load data utilizing alternating time intervals |
July 23, 2002 |
| A method for converting a distance of dependency (DoD) value to a cycle of dependency (CoD) value is disclosed. The method comprises the steps of (i) simulating a dependency system timer (DST) on a data processing system, with the DST having a present time measured in cycles and a period |
| 6418514 |
Removal of posted operations from cache operations queue |
July 9, 2002 |
| A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or mor |
| 6415424 |
Multiprocessor system with a high performance integrated distributed switch (IDS) controller |
July 2, 2002 |
| A data processing system having a modified processor chip and external components to the processor chip. The processor chip is interconnected to the external components via point-to-point bus connections controlled by an integrated distributed switch (IDS) controller. The IDS controller |
| 6415358 |
Cache coherency protocol having an imprecise hovering (H) state for instructions and data |
July 2, 2002 |
| A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of processors that are each associated with a respective one of a plurality of caches. According to the method, a first data item is stored in a fi |
| 6397320 |
Method for just-in-time delivery of load data via cycle of dependency |
May 28, 2002 |
| A method for ordering the time of issuing of a load instruction from a lower level (L2) cache controller to its L2 cache in a data processing system to enable delivery of a load data at a time it is required by its downstream dependency is disclosed. The method comprises the steps of (i) |
| 6393553 |
Acknowledgement mechanism for just-in-time delivery of load data |
May 21, 2002 |
| A system which permits dynamic verification of the availability of a desired time at which to load a data requested by a load instruction. The system comprises (i) means for appending a time dependency value to the load instruction, where the time dependency value corresponds to the |
| 6389529 |
Method for alternate preferred time delivery of load data |
May 14, 2002 |
| A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. Th |
| 6374330 |
Cache-coherency protocol with upstream undefined state |
April 16, 2002 |
| A method of maintaining cache-coherency in a multi-processor computer system provides new states to indicate that a sector in an upstream cache has been modified, without executing unnecessary bus transactions for the lower-level cache(s). These new "U" states can indicate which sector i |
