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Lesot; Jean-Philippe
Etrelles, FR
No. of patents:

Patent Number Title Of Patent Date Issued
8190861 Micro-sequence based security model May 29, 2012
A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex se
8078842 Removing local RAM size limitations when executing software code December 13, 2011
An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions
8046748 Method and system to emulate an M-bit instruction set October 25, 2011
A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a tabl
8032891 Energy-aware scheduling of application execution October 4, 2011
A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodimen
8024716 Method and apparatus for code optimization September 20, 2011
A system comprising a compiler that compiles source-level code to generate an intermediate-level instruction comprising a predetermined component. The intermediate-level instruction is an at least partially optimized version of the source-level code. Execution of the predetermined co
7941790 Data processing apparatus, system and method May 10, 2011
A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code
7757223 Method and system to construct a data-flow analyzer for a bytecode verifier July 13, 2010
The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the
7752610 Method and system for thread abstraction July 6, 2010
Systems, methods, and computer-readable media supporting thread abstraction in Java are provided. In some illustrative embodiments, a system is provided that includes a Java execution flow class that represents an execution flow context, an execution flow scheduler object including a
7743384 Method and system for implementing an interrupt handler June 22, 2010
A system for interrupt handling in Java is provided that includes an execution flow class, an execution flow scheduler, a Java virtual machine (JVM), and an interrupt handler class that extends the execution flow class. The execution flow class defines an execution flow execution met
7606977 Context save and restore with a stack-based memory structure October 20, 2009
A multi-threaded processor adapted to couple to external memory comprises a controller and data storage operated by the controller. The data storage comprises a first portion and a second portion, and wherein only one of the first or second portions is active at a time, the non-active
7565385 Embedded garbage collection July 21, 2009
An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded
7546437 Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses June 9, 2009
A processor adapted to couple to external memory. The processor comprises a controller and data storage (e.g., cache memory). The data storage is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy
7543285 Method and system of adaptive dynamic compiler resolution June 2, 2009
A method and system of adaptive dynamic compiler resolution. At least some of the illustrative embodiments are a computer-implemented method comprising compiling a source file containing an application program (the application program comprising a method, and wherein the compiling cr
7533250 Automatic operand load, modify and store May 12, 2009
A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a firs
7496930 Accessing device driver memory in programming language representation February 24, 2009
In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the applica
7493476 Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence February 17, 2009
A processor is provided that includes decode logic coupled to an instruction cache and a micro-sequence vector table including entries for each bytecode in an instruction set of the processor. The processor also includes a register coupled to the decode logic, wherein the register is
7330937 Management of stack-based memory usage in a processor February 12, 2008
A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as either a cache or scra
7260682 Cache memory usable as scratch pad storage August 21, 2007
A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the externa

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