| Patent Number |
Title Of Patent |
Date Issued |
| 6295623 |
System for testing real and simulated versions of an integrated circuit |
September 25, 2001 |
| A system for testing both simulated and real versions of an integrated circuit (IC) includes an IC simulator, a simulator manager, an IC tester, and a tester manager. The IC simulator simulates response of the IC to a set of simulated IC input signals by producing a set of simulated IC |
| 6101622 |
Asynchronous integrated circuit tester |
August 8, 2000 |
| An asynchronous integrated circuit (IC) tester includes a set of channels interconnected by a runtime bus. Each channel accesses a separate terminal of an IC device under test (DUT) for carrying out test activities during successive cycles of a test. During each cycle of a test, each cha |
| 5994938 |
Self-calibrating programmable phase shifter |
November 30, 1999 |
| A self-calibrating programmable phase shifter includes a tapped delay line for successively delaying a periodic reference signal to produce a set of phase distributed tap signals. A multiplexer selects one of the tap signals as input to a programmable delay circuit which further delays t |
| 5935256 |
Parallel processing integrated circuit tester |
August 10, 1999 |
| An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output s |
| 5931953 |
Parallel processing integrated circuit tester |
August 3, 1999 |
| An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output s |
| 5931952 |
Parallel processing integrated circuit tester |
August 3, 1999 |
| An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output s |
| 5748642 |
Parallel processing integrated circuit tester |
May 5, 1998 |
| An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output s |
| 5696772 |
Test vector compression/decompression system for parallel processing integrated circuit tester |
December 9, 1997 |
| An integrated circuit (IC) tester includes several processing nodes, each accessing a separate terminal of an IC to be tested. The tester receives as input a description of an integrated circuit test to be conducted. The description indicates actions to be taken at each processing node a |
| 5689690 |
Timing signal generator |
November 18, 1997 |
| A timing signal generator includes a voltage controlled oscillator (VCO), a logic circuit, N set circuits and N reset circuits and a bistable latch circuit. The VCO produces a set of N reference signals frequency locked to a reference clock signal and distributed in phase so as to evenly |
| 5552733 |
Precise and agile timing signal generator based on a retriggered oscillator |
September 3, 1996 |
| A timing signal generator produces a timing signal having one or more pulses of adjustable phase relative to pulses of a stable reference clock. The timing signal generator employs a low jitter retriggerable oscillator to produce a set of tap signals. The tap signals are frequency locked |
| 5345186 |
Retriggered oscillator for jitter-free phase locked loop frequency synthesis |
September 6, 1994 |
| An embodiment of the present invention is a retriggered oscillator timebase including a phase lock loop controlled ring for direct retriggering by a reference oscillator. The ring has taps at various successive stages that are output to an on-the-fly selector that can add any ten-bit val |
