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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lee; Yu-Hua
Address:
Hsinchu, TW
No. of patents:
44
Patents:












Patent Number Title Of Patent Date Issued
7482278 Key-hole free process for high aspect ratio gap filling with reentrant spacer January 27, 2009
A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern,
7160811 Laminated silicate glass layer etch stop method for fabricating microelectronic product January 9, 2007
A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned salicide blocking dielectr
7056821 Method for manufacturing dual damascene structure with a trench formed first June 6, 2006
A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, an
7015129 Bond pad scheme for Cu process March 21, 2006
A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads d
6956254 Multilayered dual bit memory device with improved write/erase characteristics and method of manu October 18, 2005
A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits col
6844626 Bond pad scheme for Cu process January 18, 2005
A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads d
6600228 Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for July 29, 2003
A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. A blanket, first photoresi
6586162 Simple photo development step to form TiSix gate in DRAM process July 1, 2003
A method of using resist planarization to prepare for silicidation while protecting silicon nitride spacers in the fabrication of integrated circuits is described. Field oxide areas are formed on a semiconductor substrate surrounding and electrically isolating a logic device area and a
6555435 Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids April 29, 2003
A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlyi
6436763 Process for making embedded DRAM circuits having capacitor under bit-line (CUB) August 20, 2002
A method for fabricating capacitor-under-bit line (CUB) DRAMs with logic circuits is achieved. CUB are better than capacitor-over-bit line (COB) DRAM circuits because of reduced contact aspect ratios, but CUB require patterning the capacitor top plate over the capacitor rough topography
6403416 Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM) June 11, 2002
A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO.sub.2) first insula
6365464 Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids April 2, 2002
A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlyi
6323118 Borderless dual damascene contact November 27, 2001
A method is disclosed for forming self-aligned, borderless contact and vias together and simultaneously with relaxed photolithographic alignment tolerances using a modified dual damascene process having two etch-stop layers. A first etch-stop layer is formed over a first dielectric layer
6307213 Method for making a fuse structure for improved repaired yields on semiconductor memory devices October 23, 2001
This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a
6294456 Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation d September 25, 2001
This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. The following steps
6274426 Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure August 14, 2001
A process for fabricating a crown shaped, capacitor structure, in a SAC opening, featuring a silicon nitride spacer, located on the walls of a bottom portion of the SAC opening, has been developed. The process features forming a SAC opening in a thick silicon oxide layer, then repair
6265315 Method for improving chemical/mechanical polish uniformity over rough topography for semiconduct July 24, 2001
A method for making a planar interlevel dielectric (ILD) layer, having improved thickness uniforming across the substrate surface, over a patterned electrically conducting layer is achieved. The method involves forming electrically conducting lines on which is deposited a conformal f
6235580 Process for forming a crown shaped capacitor structure for a DRAM device May 22, 2001
A process for forming crown shaped capacitor structures, for a DRAM device, has been developed. The process features the use of a disposable insulator layer, applied prior to photolithographic and dry etching procedures, used to define the capacitor upper plate structures. The disposable
6228736 Modified method for forming cylinder-shaped capacitors for dynamic random access memory (DRAM) May 8, 2001
A modified method for forming cylinder-shaped stacked capacitors for DRAMs which circumvents oxide erosion due to misalignment is described. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. A silicon nitride (Si.sub.3 N.sub.4) etch-stop layer is depo
6194234 Method to evaluate hemisperical grain (HSG) polysilicon surface February 27, 2001
A new method based on measuring the weight of a wafer (on which the layer of HSG has been deposited) before (W1) and after (W2) the surface of the HSG layer is coated with a layer of either photoresist or SOG. The difference delta W=W2-W1 provides an indicator of the roughness or smo
6187659 Node process integration technology to improve data retention for logic based embedded dram February 13, 2001
A new method is provided to create a gradated dopant concentration in the contact plug of DRAM devices whereby a high dopant concentration is present at the bottom of the plug and a low dopant concentration is present at the top of the plug. Two layers of dielectric are deposited; th
6165839 Process to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic December 26, 2000
A process for forming a DRAM, cylindrical shaped, stacked capacitor structure, located under a bit line structure, has been developed. The process features defining a polysilicon cell plate structure, during the same photolithotgraphic and anisotropic etching procedures, used to open a
6162686 Method for forming a fuse in integrated circuit application December 19, 2000
A method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area 14 and in product device areas. A key point of the invention is to form fuses from the via plug layer, not from the metal layers. Also, key guard rings are formed around the p
6136695 Method for fabricating a self-aligned contact October 24, 2000
A method for forming a self aligned contact wherein a dielectric layer is formed directly on a conductive structure according the present invention. A semiconductor structure having a polysilicon conductive structure (such as a bit line) thereon is provided. A contact area is located on
6121073 Method for making a fuse structure for improved repaired yields on semiconductor memory devices September 19, 2000
This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a
6107155 Method for making a more reliable storage capacitor for dynamic random access memory (DRAM) August 22, 2000
A modified method for forming stacked capacitors for DRAMs which circumvents oxide erosion due to misalignment is described. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. First openings are etched for capacitor node contacts. A polysilicon lay
6103630 Adding SF.sub.6 gas to improve metal undercut for hardmask metal etching August 15, 2000
A new method of etching metal lines using SF.sub.6 gas during the overetch step to prevent undercutting of the anti-reflective coating layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered
6103455 Method to form a recess free deep contact August 15, 2000
A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact photoresist layer 36 is formed over
6100116 Method to form a protected metal fuse August 8, 2000
A method for forming protection layers completely around a metal fuse to protect the metal fuse 74A and metal lines 74B from moisture corrosion from fuse opening and micro-cracks in dielectric layers. The invention surrounds the fuse on all sides with two protection layers: a bottom
6077738 Inter-level dielectric planarization approach for a DRAM crown capacitor process June 20, 2000
A process for obtaining global planarization, or a smooth top surface topography, for an insulator layer overlying a semiconductor chip, with DRAM device structures, featuring crown shaped capacitor structures, and with peripheral, non-DRAM devices, has been developed. The process fe
6042999 Robust dual damascene process March 28, 2000
A robust dual damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening
6037213 Method for making cylinder-shaped capacitors for dynamic random access memory March 14, 2000
A method for making cylinder-shaped stacked capacitors for DRAMs is described. A planar first insulating layer is formed over device areas. An etch-stop layer, a second insulating layer, and a polish-back endpoint detect layer are deposited in which cylinder-shaped capacitors with node
6033981 Keyhole-free process for high aspect ratio gap filing March 7, 2000
A method to eliminate voids in the dielectric oxide between closely spaced conducting lines is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A high density plasma (HDP) dielectric layer is deposited overlying the conductive lines and t
6020236 Method to form capacitance node contacts with improved isolation in a DRAM process February 1, 2000
A method to form capacitance node contacts with improved isolation in a DRAM process is described. An isolation layer is formed on a semiconductor substrate. A first contact hole is formed and filled with a polysilicon plug and the top surface of the isolation layer and of the polysilico
6017824 Passivation etching procedure, using a polysilicon stop layer, for repairing embedded DRAM cells January 25, 2000
A process of opening, a stack of large diameter via holes, in a multiple levels of insulator layers, to be used for access of a laser repair procedure, applied to underlying integrated circuit shapes, while simultaneously opening small diameter via holes, in the same multiple levels
6015734 Method for improving the yield on dynamic random access memory (DRAM) with cylindrical capacitor January 18, 2000
A new method for forming stacked capacitors for DRAMs having improved yields when the bottom electrode is misaligned to the node contact is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer, a Si.sub.3 N.sub.4 etch-stop layer, and a disposable second insulating layer
6015733 Process to form a crown capacitor structure for a dynamic random access memory cell January 18, 2000
A process for forming a crown shaped, polysilicon storage node structure, for a DRAM capacitor structure, has been developed. The process features the deposition of a polysilicon layer, on the top surface of a thick insulator layer, as well as on all surfaces of an opening, in the thick
6013550 Method to define a crown shaped storage node structure, and an underlying conductive plug struct January 11, 2000
A process for forming a crown shaped storage node structure, for a DRAM capacitor structure, has been developed. The process features the patterning of a top portion, of a storage node contact plug structure, after patterning of the crown shaped storage node structure, and after remo
5989954 Method for forming a cylinder capacitor in the dram process November 23, 1999
A method for fabricating a cylindrical capacitor is described. Semiconductor device structures, including a capacitor node contact region, are formed on a semiconductor substrate. A first insulating layer is deposited over the device structures and planarized. A silicon nitride layer
5989784 Etch recipe for embedded DRAM passivation with etch stopping layer scheme November 23, 1999
A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconduct
5985765 Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation November 16, 1999
A method for reducing bonding pad loss is achieved using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to prov
5854119 Robust method of forming a cylinder capacitor for DRAM circuits December 29, 1998
A method of forming a capacitor for DRAM or other circuits is described which avoids the problem of weak spots or gaps forming between a polysilicon contact plug and the first capacitor plate. A layer of first dielectric is formed on a substrate, A layer of second dielectric is forme
5597754 Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition a January 28, 1997
A process for fabricating a stacked capacitor, DRAM, device, with an optimized lower electrode structure, has been developed. The surface area of the lower electrode has been increased by using a specific polysilicon deposition process, featuring the use of Si2H6, followed by specific
5429979 Method of forming a dram cell having a ring-type stacked capacitor July 4, 1995
A new method for fabricating a storage capacitor, on a dynamic random access memory (DRAM) cell, having a ring-type sidewall was accomplished. The method involves opening the self-aligned node contact to the source/drain area of the field effect transistor and forming the bottom capa










 
 
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