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Inventor:
Lee; Seung-hwan
Address:
Suwon-si, KR
No. of patents:
16
Patents:












Patent Number Title Of Patent Date Issued
8269840 Image stabilization driving assembly September 18, 2012
An image stabilization driving assembly that corrects a shake of a digital camera includes a driving plate in which a correction lens is mounted and that operates in a direction perpendicular to an optical axis; a base plate that supports the driving plate at a rear of the driving pl
8114735 Method of manufacturing a non-volatile memory device February 14, 2012
In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat trea
8105930 Method of forming dielectric including dysprosium and scandium by atomic layer deposition and in January 31, 2012
In one embodiment, the method of forming a dielectric layer includes supplying a first precursor at a temperature less than 400 degrees Celsius to a chamber including a substrate. The first precursor includes dysprosium. A first reaction gas is supplied to the chamber to react with t
7927950 Method of fabricating trap type nonvolatile memory device April 19, 2011
A method of fabricating a floating trap type nonvolatile memory device includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequenti
7863152 Semiconductor device structure with strain layer and method of fabricating the semiconductor dev January 4, 2011
A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dumm
7714394 CMOS semiconductor devices having elevated source and drain regions and methods of fabricating t May 11, 2010
A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regi
7682906 Method of manufacturing a non-volatile memory device March 23, 2010
A method of manufacturing a non-volatile memory device includes forming a tunnel isolation layer forming a tunnel isolation layer on a substrate, forming a conductive pattern on the tunnel isolation layer, forming a lower silicon oxide layer on the conductive pattern, treating a surface
7671420 Semiconductor devices having faceted channels and methods of fabricating such devices March 2, 2010
Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orient
7635633 Non-volatile memory device and method of manufacturing the same December 22, 2009
In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patte
7619285 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby November 17, 2009
A CMOS transistor includes first and second conductivity type MOS transistors. The first conductivity type MOS transistor includes elevated source and drain regions which abut a channel region in a semiconductor substrate and which are formed by elevated epitaxial layers, each includ
7605067 Method of manufacturing non-volatile memory device October 20, 2009
A method of manufacturing a non-volatile memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density
7601983 Transistor and method of manufacturing the same October 13, 2009
A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second
7517750 Flash memory devices having multilayered inter-gate dielectric layers including metal oxide laye April 14, 2009
Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active r
7510931 Method of fabricating a nonvolatile memory device March 31, 2009
A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a first charge blocking layer on the charge trapping layer by supplying a metal source ga
7365010 Semiconductor device having carbon-containing metal silicide layer and method of fabricating the April 29, 2008
Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electrode and source/drain
7354835 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby April 8, 2008
In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the










 
 
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