| Patent Number |
Title Of Patent |
Date Issued |
| 5051896 |
Apparatus and method for nullifying delayed slot instructions in a pipelined computer system |
September 24, 1991 |
| In a computing system which has memory and an instruction pipeline, a method and apparatus allows for nullification of a second instruction responsive to the state of a nullification field in a first instruction executed prior to the second instruction. After the first instruction is |
| 4928239 |
Cache memory with variable fetch and replacement schemes |
May 22, 1990 |
| An instruction is presented to the cache; the instruction includes a cache control specifier which identifies a type of data being requested. Based on the cache control specifier, one of a plurality of replacement schemes is selected for swapping a data block out of the cache. |
| 4829424 |
Maximal length immediates with fixed sign position |
May 9, 1989 |
| A computer instruction set is presented in accordance with the preferred embodiment of the present invention. Some instructions within the instruction set have immediate fields which are allowed to vary in length and fill up all unused bit positions in the instructions. A sign bit is in |
| 4763242 |
Computer providing flexible processor extension, flexible instruction set extension, and implici |
August 9, 1988 |
| A computer and an instruction set are presented which allow for a number of assists to be easily incorporated into the computer, and which allow for an instruction set extension. The computer is designed to support instructions which move data between an assist and a location, although a |
| 4755966 |
Bidirectional branch prediction and optimization |
July 5, 1988 |
| A method and apparatus for efficient branching within a central processing unit with overlapped fetch and execute cycles which optimizes the efficient fetching of instructions. |
| 4722050 |
Method and apparatus for facilitating instruction processing of a digital computer |
January 26, 1988 |
| A computer having a cache memory and a main memory is provided with a transformation unit between the main memory and the cache memory so that at least a portion of an information unit retrieved from the main memory may be transformed during retrieval of the information (fetch) from a ma |
