| Patent Number |
Title Of Patent |
Date Issued |
| 5991880 |
Overridable data protection mechanism for PLDs |
November 23, 1999 |
| An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator |
| 5949987 |
Efficient in-system programming structure and method for non-volatile programmable logic devices |
September 7, 1999 |
| An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data |
| 5838901 |
Overridable data protection mechanism for PLDs |
November 17, 1998 |
| An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator |
| 5801548 |
Configurable performance-optimized programmable logic device |
September 1, 1998 |
| A programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production, and for allowing the PLD to selectively operate on either a 3.3-volt or a 5-volt power supply. The configurable circuitry includes an in |
| 5764076 |
Circuit for partially reprogramming an operational programmable logic device |
June 9, 1998 |
| A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic |
| 5734868 |
Efficient in-system programming structure and method for non-volatile programmable logic devices |
March 31, 1998 |
| An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data |
| 5689516 |
Reset circuit for a programmable logic device |
November 18, 1997 |
| A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, no |
| 5661685 |
Programmable logic device with configurable power supply |
August 26, 1997 |
| An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power |
| 5631583 |
Sense amplifier for programmable logic device having selectable power modes |
May 20, 1997 |
| A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed |
| 5617041 |
Method and apparatus for reducing coupling switching noise in interconnect array matrix |
April 1, 1997 |
| In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interc |
| 5563827 |
Wordline driver for flash PLD |
October 8, 1996 |
| A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an invert |
| 5530384 |
Sense amplifier having selectable power and speed modes |
June 25, 1996 |
| A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed |
| 5526322 |
Low-power memory device with accelerated sense amplifiers |
June 11, 1996 |
| An AND array for an erasable programmable logic device (EPLD) includes word-line transition detectors for indicating high-to-low word-line transitions. Such transitions are a condition precedent for low to-high bit line transitions. Transition indications are buffered by a fast trans |
| 5524097 |
Power saving sense amplifier that mimics non-toggling bitline states |
June 4, 1996 |
| A sense amplifier of the present invention provides power savings of between 30% to 70% for typical usage of a programmable logic device. In one embodiment, this sense amplifier includes circuitry for detecting and propagating the logic state on a bit line, an amplifier for amplifying th |
