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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lee; Nae-in
Address:
Seoul, KR
No. of patents:
40
Patents:












Patent Number Title Of Patent Date Issued
8232613 Germanium silicide layer including vanadium, platinum, and nickel July 31, 2012
Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include form
7902609 Semiconductor devices including multiple stress films in interface area March 8, 2011
A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and
7902019 Dielectric layer for semiconductor device and method of manufacturing the same March 8, 2011
A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.
7863142 Method of forming a germanium silicide layer, semiconductor device including the germanium silic January 4, 2011
Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include form
7785951 Methods of forming integrated circuit devices having tensile and compressive stress layers there August 31, 2010
Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a
7759185 Semiconductor device and method of fabricating the same July 20, 2010
A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain
7642148 Methods of producing semiconductor devices including multiple stress films in interface area January 5, 2010
A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and
7642140 CMOS integrated circuit devices and substrates having buried silicon germanium layers therein an January 5, 2010
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si.sub.1-xGe.sub.x layer is also d
7595253 Method of forming the semiconductor device September 29, 2009
Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity a
7494940 Post thermal treatment methods of forming high dielectric layers over interfacial layers in inte February 24, 2009
High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, an
7371633 Dielectric layer for semiconductor device and method of manufacturing the same May 13, 2008
A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.
7250655 MOS transistor having a T-shaped gate electrode July 31, 2007
A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surfa
7195987 Methods of forming CMOS integrated circuit devices and substrates having buried silicon germaniu March 27, 2007
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si.sub.1-xGe.sub.x layer is also d
7112539 Dielectric layer for semiconductor device and method of manufacturing the same September 26, 2006
A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The
7092298 Methods of erasing a non-volatile memory device having discrete charge trap sites August 15, 2006
Methods of erasing a non-volatile memory device having discrete charge trap sites between a semiconductor substrate and a gate include applying a negative voltage to a gate at least partially spaced apart from a semiconductor substrate by a charge storage layer providing discrete cha
7060563 Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturi June 13, 2006
A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the
7037863 Post thermal treatment methods of forming high dielectric layers over interfacial layers in inte May 2, 2006
High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, an
6998309 Method of manufacturing a non-volatile semiconductor memory device February 14, 2006
A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to
6917085 Semiconductor transistor using L-shaped spacer July 12, 2005
The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped
6914301 CMOS integrated circuit devices and substrates having buried silicon germanium layers therein an July 5, 2005
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si.sub.1-x Ge.sub.x layer is also
6884705 Semiconductor device having hetero grain stack gate and method of forming the same April 26, 2005
A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the ga
6881650 Method for forming SOI substrate April 19, 2005
A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a porous silicon-germa
6881621 Method of fabricating SOI substrate having an etch stop layer, and method of fabricating SOI int April 19, 2005
A method of fabricating a SOI substrate includes sequentially forming a first semiconductor layer, which may be either a porous semiconductor layer or a bubble layer, a second semiconductor layer and a buried oxide layer on a front surface of a semiconductor substrate, forming an etch
6878580 Semiconductor device having gate with negative slope and method for manufacturing the same April 12, 2005
A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed
6875678 Post thermal treatment methods of forming high dielectric layers in integrated circuit devices April 5, 2005
High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and ann
6844604 Dielectric layer for semiconductor device and method of manufacturing the same January 18, 2005
A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The
6815764 Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturi November 9, 2004
A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the
6806517 Flash memory having local SONOS structure using notched gate and manufacturing method thereof October 19, 2004
A notched gate SONOS transistor includes: a substrate having source/drain regions; a gate insulator layer on the substrate between the source/drain regions; a notched gate structure, on the gate insulator leyer, having at least one notch; and at least one ONO wedge structure in the at le
6794306 Semiconductor device having gate all around type transistor and method of forming the same September 21, 2004
A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon ge
6750532 CMOS semiconductor device and method of manufacturing the same June 15, 2004
In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMO
6727130 Method of forming a CMOS type semiconductor device having dual gates April 27, 2004
A method of forming a CMOS type semiconductor device having dual gate includes forming a first gate insulation layer and a first metal-containing layer sequentially on a surface of a substrate in first and second impurity type transistor regions, removing the first metal-containing l
6716689 MOS transistor having a T-shaped gate electrode and method for fabricating the same April 6, 2004
A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface
6693013 Semiconductor transistor using L-shaped spacer and method of fabricating the same February 17, 2004
The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a h
6670677 SOI substrate having an etch stop layer and an SOI integrated circuit fabricated thereon December 30, 2003
A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer a
6667525 Semiconductor device having hetero grain stack gate December 23, 2003
A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the ga
6633066 CMOS integrated circuit devices and substrates having unstrained silicon active layers October 14, 2003
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si.sub.1-x Ge.sub.x layer is also
6605847 Semiconductor device having gate all around type transistor and method of forming the same August 12, 2003
A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon ge
6541822 Method of manufacturing an SOI type semiconductor that can restrain floating body effect April 1, 2003
A method of forming a SOI type semiconductor device comprises forming a first trench in a SOI layer forming a portion of an isolation layer region between an element region and a ground region by etching the SOI layer of a SOI type substrate using an etch stop layer pattern as an etch ma
6524902 Method of manufacturing CMOS semiconductor device February 25, 2003
In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMO
6486039 Method of fabricating a trench isolation structure having sidewall oxide layers with different t November 26, 2002
A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted a










 
 
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