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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lee; Jongwook
Address:
Yongin-si, KR
No. of patents:
28
Patents:












Patent Number Title Of Patent Date Issued
8294209 Semiconductor memory device and method of manufacturing the same October 23, 2012
A semiconductor memory device includes a plurality of active pillars protruding from a semiconductor substrate, a first gate electrode disposed on at least one sidewall of the active pillar, a first gate insulating layer being disposed between the active pillar and the first gate ele
8273620 Semiconductor integrated circuit device and related fabrication method September 25, 2012
Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripher
8236650 Vertical-type non-volatile memory devices and methods of manufacturing the same August 7, 2012
In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided,
8163616 Methods of manufacturing nonvolatile memory devices April 24, 2012
Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates connected to
8101509 Semiconductor integrated circuit device January 24, 2012
A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric
8063441 Vertical type semiconductor device November 22, 2011
A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresp
8063438 Vertical-type semiconductor devices November 22, 2011
In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewall
7960780 Vertical-type semiconductor device June 14, 2011
In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the
7956407 Vertical type semiconductor device, method of manufacturing a vertical type semiconductor device June 7, 2011
A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity
7888246 Semiconductor integrated circuit device and a method of fabricating the same February 15, 2011
A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric
7871906 Storage nodes including a phase chang layer and methods of manufacturing and operating the same, January 18, 2011
In various embodiments, the present disclosure may provide a storage node. In various implementations, the storage node may include a bottom electrode having a non-planar bottom surface that conforms with and is connected to a non-planar top surface of a diode electrode of a memory d
7851327 Method of manufacturing a semiconductor device including forming a single-crystalline semiconduc December 14, 2010
In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are
7799648 Method of forming a MOSFET on a strained silicon layer September 21, 2010
A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is
7755133 Semiconductor integrated circuit device and related fabrication method July 13, 2010
Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripher
7704843 Method of manufacturing a semiconductor device April 27, 2010
In a semiconductor device and a method of manufacturing the same, a conductive structure is formed on an active region defined by a device isolation layer on a semiconductor substrate. The conductive structure includes a gate pattern and source/drain regions adjacent to the gate patt
7700461 Methods of laterally forming single crystalline thin film regions from seed layers April 20, 2010
In a method of manufacturing a semiconductor device, a string structure including a selection transistor and a memory cell on a substrate. An insulation layer pattern is formed on the substrate to cover the string structure. The insulation layer pattern includes at least one opening
7679133 Vertical-type non-volatile memory devices March 16, 2010
In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided,
7652340 Fin field effect transistor and method of manufacturing the same January 26, 2010
In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon
7557388 MOSFET formed on a strained silicon layer July 7, 2009
A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is
7553742 Method(s) of forming a thin layer June 30, 2009
A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insul
7537980 Method of manufacturing a stacked semiconductor device May 26, 2009
In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern having a first opening may be formed on the seed layer. A first SEG process may be carried out to form a first plug partially fillin
7501674 Semiconductor device having fin transistor and planar transistor and associated methods of manuf March 10, 2009
Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transist
7442596 Methods of manufacturing fin type field effect transistors October 28, 2008
A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the su
7422965 Methods of fabricating p-type transistors including germanium channel regions September 9, 2008
A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-c
7396761 Semiconductor device and method of manufacturing the same July 8, 2008
In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is
7364990 Epitaxial crystal growth process in the manufacturing of a semiconductor device April 29, 2008
First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection stru
7326608 Fin field effect transistor and method of manufacturing the same February 5, 2008
In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon
7315063 CMOS transistor and method of manufacturing the same January 1, 2008
A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conducti










 
 
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