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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lee; Brian S.
Address:
Hsinchu, TW
No. of patents:
10
Patents:




Patent Number Title Of Patent Date Issued
7402364 Semiconductor device with loop line pattern structure, method and alternating phase shift mask f July 22, 2008
An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180.degree. phase difference from second regions with 0.degr
7087947 Semiconductor device with loop line pattern structure, method and alternating phase shift mask f August 8, 2006
An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180.degree. phase difference from second regions with 0.degr
6828615 Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory December 7, 2004
A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that req
6818515 Method for fabricating semiconductor device with loop line pattern structure November 16, 2004
An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180.degree. phase difference from second regions with 0.degr
6770954 Semiconductor device with SI-GE layer-containing low resistance, tunable contact August 3, 2004
The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a Si.sub.x Ge.sub.1-x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The
6703279 Semiconductor device having contact of Si-Ge combined with cobalt silicide March 9, 2004
The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt layer can serve as a glue layer and d
6566190 Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory May 20, 2003
A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that req
6544888 Advanced contact integration scheme for deep-sub-150 nm devices April 8, 2003
An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes with a process employing a W-Salicid
6521956 Semiconductor device having contact of Si-Ge combined with cobalt silicide February 18, 2003
The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt layer can serve as a glue layer and d
6511905 Semiconductor device with Si-Ge layer-containing low resistance, tunable contact January 28, 2003
The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a Si.sub.x Ge.sub.1-x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The


 
 
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