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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Le; Hung Qui
Address:
Austin, TX
No. of patents:
82
Patents:


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Patent Number Title Of Patent Date Issued
8117403 Transactional memory system which employs thread assists using address history tables February 14, 2012
A computing system uses specialized "Set Associative Transaction Tables" and additional "Summary Transaction Tables" to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table and processes memory transaction
8108655 Selecting fixed-point instructions to issue on load-store unit January 31, 2012
Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue log
7904661 Data stream prefetching in a microprocessor March 8, 2011
A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associate
7877580 Branch lookahead prefetch for microprocessors January 25, 2011
A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions
7827443 Processor instruction retry recovery November 2, 2010
Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the
7716427 Store stream prefetching in a microprocessor May 11, 2010
In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The
7650486 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions January 19, 2010
A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads
7631308 Thread priority method for ensuring processing fairness in simultaneous multi-threading micropro December 8, 2009
A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread dur
7620799 Using a modified value GPR to enhance lookahead prefetch November 17, 2009
Mechanisms to identify and speculatively execute future instructions during a stall condition are provided. In speculative mode, instruction operands may be invalid due to a number of reasons. Dependency and dirty bits are tracked and used to determine which speculative instructions are
7603543 Method, apparatus and program product for enhancing performance of an in-order processor with lo October 13, 2009
A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention compr
7600099 System and method for predictive early allocation of stores in a microprocessor October 6, 2009
A system and method for predictive early allocation of stores in a microprocessor is presented. During instruction dispatch, an instruction dispatch unit retrieves an instruction from an instruction cache (Icache). When the retrieved instruction is an interruptible instruction, the i
7594096 Load lookahead prefetch for microprocessors September 22, 2009
The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or t
7552318 Branch lookahead prefetch for microprocessors June 23, 2009
A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions
7551475 Data shifting through scan registers June 23, 2009
A circuit permits a user to present signals to control the flow of data from a first-type cell to a second-type cell. The circuit is susceptible to loading each cell individually, as well as loading cells by means of scanning input in a series through a low order cell to a higher order
7490226 Method using vector component comprising first and second bits to regulate movement of dependent February 10, 2009
A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing
7487334 Branch encoding before instruction cache write February 3, 2009
Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch p
7478276 Method for checkpointing instruction groups with out-of-order floating point instructions in a m January 13, 2009
A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemente
7475223 Fetch-side instruction dispatch group formation January 6, 2009
An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping of instructions pr
7467325 Processor instruction retry recovery December 16, 2008
Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the
7444498 Load lookahead prefetch for microprocessors October 28, 2008
The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or t
7421567 Using a modified value GPR to enhance lookahead prefetch September 2, 2008
The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread
7380066 Store stream prefetching in a microprocessor May 27, 2008
In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The
7350029 Data stream prefetching in a microprocessor March 25, 2008
A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associate
7302553 Apparatus, system and method for quickly determining an oldest instruction in a non-moving instr November 27, 2007
An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a present status of the i
7269715 Instruction grouping history on fetch-side dispatch group formation September 11, 2007
An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current set of instructions
7254697 Method and apparatus for dynamic modification of microprocessor instruction group at dispatch August 7, 2007
Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few as one instruction
7237094 Instruction group formation and mechanism for SMT dispatch June 26, 2007
A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating
7080241 Mechanism for self-initiated instruction issuing and method therefor July 18, 2006
An apparatus and method for self-initiated instruction issuing are implemented. In a central processing unit (CPU) having a pipelined architecture, instructions are queued for issuing to the execution unit which will execute them. Instructions are issued each cycle, and an instructio
7051177 Method for measuring memory latency in a hierarchical memory system May 23, 2006
A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a
7047398 Analyzing instruction completion delays in a processor May 16, 2006
A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of compl
6970999 Counting latencies of an instruction table flush, refill and instruction execution using a plura November 29, 2005
A method and system for analyzing cycles per instruction (CPI) performance in a processor. A completion table corresponds to the instructions in a group to be processed by the processor. An empty completion table indicates that there has been some type of catastrophe that caused a table
6910120 Speculative counting of performance events with rewind counter June 21, 2005
A circuit and method for maintaining a correct value in performance monitor counter within a speculative computer microprocessor is disclosed. In response to determining the begin of speculative execution within the microprocessor, the value of the performance monitor counter is stored i
6898696 Method and system for efficiently restoring a processor's execution state following an interrupt May 24, 2005
A method and system for increasing the efficiency of execution in a processor. Instructions are dispatched in instruction groups, wherein if such an instruction group contains an interruptible instruction of a selected type, only one interruptible instruction of the selected type is
6826678 Completion monitoring in a processor having multiple execution units with various latencies November 30, 2004
A method, processor architecture, computer program product, and data processing system for determining when an instruction in a pipelined processor should be completed is provided. As each instruction is issued to an execution unit, an entry for that instruction is placed within a "f
6721874 Method and system for dynamically shared completion table supporting multiple threads in a proce April 13, 2004
A method and system for utilizing a completion table in a superscalar processor is disclosed. The method and system comprises providing a plurality of threads to the processor and associating a link list with each of the threads, wherein each entry associated with a thread is linked
6658555 Determining successful completion of an instruction by comparing the number of pending instructi December 2, 2003
A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instructio
6658534 Mechanism to reduce instruction cache miss penalties and methods therefor December 2, 2003
The mechanism to reduce instruction cache miss penalties by initiating an early cache line prefetch is implemented. The mechanism provides for an early prefetch of a next succeeding cache line before an instruction cache miss is detected during a fetch which causes an instruction cache m
6654876 System for rejecting and reissuing instructions after a variable delay time period November 25, 2003
A method, processor, and data processing system implementing a delayed reject mechanism are disclosed. The processor includes an issue unit suitable for issuing an instruction in a first cycle and a load store unit (LSU). The LSU includes an extend reject calculator circuit configured to
6654869 Assigning a group tag to an instruction group wherein the group tag is recorded in the completio November 25, 2003
A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of i
6631463 Method and apparatus for patching problematic instructions in a microprocessor using software in October 7, 2003
A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instructi
6553480 System and method for managing the execution of instruction groups having multiple executable in April 22, 2003
A group completion table (GCT) that manages the execution of instruction groups having more than one executable instruction is disclosed. The GCT includes a plurality of table entries, wherein each of the table entries is associated with a respective instruction group. Each table entry i
6543003 Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor April 1, 2003
A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.
6543002 Recovery from hang condition in a microprocessor April 1, 2003
A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion
6535973 Method and system for speculatively issuing instructions March 18, 2003
A method and system for speculatively issuing instructions which are dependent upon results from execution of other instructions. Instructions are speculatively issued, dependent upon a result from execution of a primary instruction, wherein the speculatively issued instructions are
6480931 Content addressable storage apparatus and register mapper architecture November 12, 2002
A non-conventional CAM (content addressable memory) and register mapper organization and circuit implementation is provided which allows simultaneous execution of a large number of CAM searches. All compare circuits are placed outside of the CAM in separate match arrays where the act
6473850 System and method for handling instructions occurring after an ISYNC instruction October 29, 2002
An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC instruction) unconditionally. The present invention detects the occurrence of any instruction that changes the state of the machine
6463524 Superscalar processor and method for incrementally issuing store instructions October 8, 2002
A superscalar processor and method are disclosed for efficiently executing a store instruction. The store instruction is stored in an issue queue within the processor. A first part of the store instruction is issued from the issue queue to a first one of different execution units in resp
6442675 Compressed string and multiple generation engine August 27, 2002
A generalized, programmable dataflow state-machine is provided to receive information about a particular string instruction. The string instruction is parsed into all the operations contained in the string instruction. The operations that make up the string instruction are routed to para
6430678 Scoreboard mechanism for serialized string operations utilizing the XER August 6, 2002
An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit
6356918 Method and system for managing registers in a data processing system supports out-of-order and s March 12, 2002
A method and a system in a data processing system for managing registers in a register array wherein the data processing system has M architected registers and the register array has greater than M registers. A first physical register address is selected from a group of available physica
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