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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Le; Hien Minh
Address:
Cedar Park, TX
No. of patents:
6
Patents:












Patent Number Title Of Patent Date Issued
8296520 System and method for optimizing neighboring cache usage in a multiprocessor environment October 23, 2012
A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least
8020058 Multi-chip digital system having a plurality of controllers with self-identifying signal September 13, 2011
The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to
7836257 System and method for cache line replacement selection in a multiprocessor environment November 16, 2010
A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whethe
7716546 System and method for improved LBIST power and run time May 11, 2010
A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the
7409469 Multi-chip digital system having a plurality of controllers with input and output pins wherein s August 5, 2008
The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to tr
7080269 Method and apparatus for implementing power-saving sleep mode in design with multiple clock doma July 18, 2006
A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states










 
 
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