| Patent Number |
Title Of Patent |
Date Issued |
| 6771554 |
Access delay test circuit for self-refreshing DRAM |
August 3, 2004 |
| An enhanced arbitration and control subsystem for a self-refreshing DRAM has a normal mode of operation and a test mode of operation in which an internal refresh cycle is automatically performed prior to each external access cycle. A first gate is opened in a normal mode of operation to |
| 6757207 |
Refresh miss detect circuit for self-refreshing DRAM |
June 29, 2004 |
| A counter is incremented whenever an internal refresh is requested and a prior internal refresh request has not yet been completed. A refresh-request storage element such as a latch circuit, provides an output signal that is set upon receipt of an internal refresh request control sig |
| 6741515 |
DRAM with total self refresh and control circuit |
May 25, 2004 |
| Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator a |
| 6721210 |
Voltage boosting circuit for a low power semiconductor memory |
April 13, 2004 |
| An improved voltage boosting circuit operates entirely from a single, common VCC voltage supply. An NMOS pass transistor has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor is connected to a |
| 6643216 |
Asynchronous queuing circuit for DRAM external RAS accesses |
November 4, 2003 |
| A method and queuing circuit are provided for storing asynchronous external RAS access requests and for executing corresponding RAS cycles. When no current external access RAS cycle is currently underway a first request latch or similar storage element is set in response to an initial ac |
