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Inventor: Lawyer; Philip H.
Address: Thousand Oaks, CA
No. of patents: 2
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 7470619 |
Interconnect with high aspect ratio plugged vias |
December 30, 2008 |
| Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coating (BARC) on the |
| 6828677 |
Precision electroplated solder bumps and method for manufacturing thereof |
December 7, 2004 |
| A solder bump structure for use on a substrate. The solder bump structure includes a multilayer underbump metallization having a major upper surface with a solder wetable caplayer for contacting a solder bump, the mutilayer underbump metallization projecting from the substrate with an ex |
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