| Patent Number |
Title Of Patent |
Date Issued |
| 7328384 |
Method and apparatus using device defects as an identifier |
February 5, 2008 |
| A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects. |
| 6882182 |
Tunable clock distribution system for reducing power dissipation |
April 19, 2005 |
| A tunable clock distribution system is used to minimize the power dissipation of a clock distribution network in an integrated circuit. The tunable clock distribution system provides a tunable inductance on the clock distribution network to adjust a resonant frequency in the tunable |
| 6381732 |
FPGA customizable to accept selected macros |
April 30, 2002 |
| A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If |
| 6357037 |
Methods to securely configure an FPGA to accept selected macros |
March 12, 2002 |
| A method is provided for configuring an FPGA to accept or reject selected software (macros). Specifically, if an end user desires to use a locked macro from a first macro vendor a locked macro from a second macro vendor in the same FPGA, a key manager prepares a keyed FPGA for the end us |
| 6324676 |
FPGA customizable to accept selected macros |
November 27, 2001 |
| A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If |
| 6324672 |
Method for configuring circuits over a data communications link |
November 27, 2001 |
| A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit- |
| 6301695 |
Methods to securely configure an FPGA using macro markers |
October 9, 2001 |
| A method is provided for securely configuring an FPGA with macros. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a marked design file containing a macro marker rather than the actual macro. The marked design file is converted into confi |
| 6172520 |
FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA |
January 9, 2001 |
| The present invention allows one portion of an FPGA to reconfigure another portion of the same FPGA. The invention makes use of input/output ports that can be connected on the input side to a frame register for loading configuration data into the FPGA. When a portion of the FPGA is to be |
| 6118938 |
Memory map computer control system for programmable ICS |
September 12, 2000 |
| A table-based computer user interface and a method of providing design parameters are provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory m |
| 6107821 |
On-chip logic analysis and method for using the same |
August 22, 2000 |
| A programmable logic device (PLD) includes a plurality of logic resources, a plurality of multi-bit configuration memories (MBCMs), and a trigger logic structure. The plurality of MBCMs include multiple memory slices that allow the PLD to switch rapidly between configurations, or context |
| 6049222 |
Configuring an FPGA using embedded memory |
April 11, 2000 |
| An FPGA includes an embedded non-volatile memory coupled to a configuration access port. The configuration access port allows the non-volatile memory to program the configuration memory of the FPGA. On power-on or reset, the non-volatile memory configures a first portion of the FPGA usin |
| 6044025 |
PROM with built-in JTAG capability for configuring FPGAs |
March 28, 2000 |
| The invention provides a structure and method for configuring an FPGA from a PROM using a boundary scan chain. A PROM is provided that comprises JTAG circuitry. Configuration data is stored in the PROM memory as in known PROMs. When the data is retrieved from the PROM memory it is provid |
| 6028445 |
Decoder structure and method for FPGA configuration |
February 22, 2000 |
| A method is provided for configuring an FPGA using a decoder implemented in the FPGA. Specifically, an external configuration device or an embedded non-volatile memory configures a first portion of the FPGA as a decoder. Encoded configuration data is transferred to the decoder, which the |
| 6023565 |
Method for configuring circuits over a data communications link |
February 8, 2000 |
| A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit- |
| 5949690 |
Schematic design entry with annotated timing |
September 7, 1999 |
| The invention provides to the user a way of ascertaining the estimated delay through a circuit, by placing a timing attribute on the schematic symbol for the circuit that automatically displays the estimated delay. Reported delays may include maximum delay, typical delay, and/or minimum |
| 5946478 |
Method for generating a secure macro element of a design for a programmable IC |
August 31, 1999 |
| A method of generating and using a secure macro element for configuring programmable ICs is provided. The method provides a bitstream to a user, rather than providing a user-editable macro. Compilation software is provided to the user that combines the data from a "macro bitstream" (the |
| 5928338 |
Method for providing temporary registers in a local bus device by reusing configuration bits oth |
July 27, 1999 |
| In PCI devices, there are bits specified as read-only for use in configuring a system upon reset that could also be used after configuration for reading and writing. The present invention allows the use of such bit locations for other arbitrary user-defined purposes such as a mailbox |
| 5870309 |
HDL design entry with annotated timing |
February 9, 1999 |
| The invention provides to the user a way of ascertaining the estimated delay through a circuit, by back-annotating the estimated delay through an instantiated macro into the HDL circuit description. Reported delays may include maximum delay, typical delay, and/or minimum delay on the cri |
| 5673198 |
Concurrent electronic circuit design and implementation |
September 30, 1997 |
| A system for providing real time design feedback to a user of a data processing system for designing an electronic circuit includes a display system, a graphical, textual or mixed user input process which displays user input on the display system for designing an electronic circuit, and |
