| Patent Number |
Title Of Patent |
Date Issued |
| 8259121 |
System and method for processing data using a network |
September 4, 2012 |
| Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates w |
| 8086870 |
Methods and apparatus for hardware normalization and denormalization |
December 27, 2011 |
| Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normalization techniques |
| 7996670 |
Classification engine in a cryptography acceleration chip |
August 9, 2011 |
| Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a |
| 7990390 |
Multi-pass system and method supporting multiple streams of video |
August 2, 2011 |
| Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on |
| 7861104 |
Methods and apparatus for collapsing interrupts |
December 28, 2010 |
| Methods and apparatus are provided for generating interrupts associated with the completion of data processing. An external host may pass a first data block to a first processing engine and later pass a second data block to a second processing engine. In typical implementations, the |
| 7853734 |
Video bus for a video decoding system |
December 14, 2010 |
| Systems and methods are disclosed for a bus, link or interface. More specifically, systems and methods are discloses for a bus, link or interface adapted to transmit data and control information to at least one processing module and provide synchronization between the data and the co |
| 7679629 |
Methods and systems for constraining a video signal |
March 16, 2010 |
| Systems and methods for filtering to comply with copy-protection regulations set forth for HDTV signals by the Motion Picture Association of America ("MPAA") are presented. A copy-protection filter constrains the resolution of the HDTV signal when copy-protection bits are present in |
| 7636125 |
Filter module for a video decoding system |
December 22, 2009 |
| Systems and methods are disclosed for filter modules in a video display system or network. One embodiment relates to a method for operating a filter module in a video display network comprising determining a picture type, display type and operation of the display network. The method |
| 7600131 |
Distributed processing in a cryptography acceleration chip |
October 6, 2009 |
| Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a |
| 7280155 |
Method and system for converting interlaced formatted video to progressive scan video |
October 9, 2007 |
| Processing video signals may comprise converting interlaced formatted video to progressive scan video by simultaneously performing: color edge detection on a first and second field; temporal filtering on the second field and third field; and 3:2 pull down detecting on the second field |
| 7113221 |
Method and system for converting interlaced formatted video to progressive scan video |
September 26, 2006 |
| Aspects of the invention include a 3:2 pull down detector coupled to a 3:2 cadence processor and a color edge detector coupled to a binder. The binder may be coupled to a 3:2 cadence processor. A filter, which may be a temporal or infinite impulse response filter, may be coupled to the |
| 7062657 |
Methods and apparatus for hardware normalization and denormalization |
June 13, 2006 |
| Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normalization techniques |
| 7057664 |
Method and system for converting interlaced formatted video to progressive scan video using a co |
June 6, 2006 |
| Aspects of the invention for converting interlace formatted video to progressive scan video, may include a color edge detector block (306) adapted to determined edges in interlaced formatted video. A threshold and gain processor block (308) coupled to the color edge detector block (3 |
| 6133901 |
Method and system for width independent antialiasing |
October 17, 2000 |
| An efficient method for width independent antialiasing of point primitives and line primitives in a frame buffer of a graphics computer system. The graphics computer system calculates an integral of an impulse response of a low pass filter. A plurality of values representative of the int |
