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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lasserre; Serge
Address:
Frejus, FR
No. of patents:
42
Patents:












Patent Number Title Of Patent Date Issued
8032891 Energy-aware scheduling of application execution October 4, 2011
A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodimen
7941790 Data processing apparatus, system and method May 10, 2011
A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code
7840784 Test and skip processor instruction having at least one register operand November 23, 2010
A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on the results of the comparison, the instruction that follows the test and skip instruction is "skipped." The test and skip i
7840782 Mixed stack-based RISC processor November 23, 2010
A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some
7757067 Pre-decoding bytecode prefixes selectively incrementing stack machine program counter July 13, 2010
A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel wit
7712098 Data transfer controlled by task attributes May 4, 2010
A digital system and method of operation is provided in which several processors (440, 450) are connected to a shared memory resource (460). Translation lookaside buffers (TLB) (400, 402) are connected to receive a request address (404a-n) from each respective processor. Each TLB has a
7634643 Stack register reference control bit in source operand of instruction December 15, 2009
A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The instruction causes the processor to perform a test using the immediate value and the contents of the register referenced in
7565385 Embedded garbage collection July 21, 2009
An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded
7555611 Memory management of local variables upon a change of context June 30, 2009
A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java local variables) may be stored in the data memory. The data memory preferably is adapted to s
7509391 Unified memory management system for multi processor heterogeneous architecture March 24, 2009
A multi-processor system 8 includes multiple processing devices, including DSPs (10), processor units (MPUs) (21), co-processors (30) and DMA channels (31). Some of the devices may include internal MMUs (19, 32) which allows the device (10, 21, 30, 31) to work with a large virtual ad
7496930 Accessing device driver memory in programming language representation February 24, 2009
In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the applica
7434029 Inter-processor control October 7, 2008
A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an unsupported instruction is detected. The second processor executes the unsupported instru
7434021 Memory allocation in a multi-processor system October 7, 2008
A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated
7386671 Smart cache June 10, 2008
A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a
7360060 Using IMPDEP2 for system commands related to Java accelerator hardware April 15, 2008
A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder coupled to the decoder, and operates in parallel with the decoder, determines the mode of o
7330937 Management of stack-based memory usage in a processor February 12, 2008
A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as either a cache or scra
6996683 Cache coherency in a multi-processor system February 7, 2006
A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also comprises a memory subsystem coupled to the first and second processors. For a write transa
6968400 Local memory with indicator bits to support concurrent DMA and CPU access November 22, 2005
A digital system is provided having at least one processor with an associated multi-segment local memory circuit. Validity circuitry is operable to indicate if each segment of the plurality of segments holds valid data. Dirty bit circuitry indicates if data within the local memory is
6826652 Smart cache November 30, 2004
A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting
6792508 Cache with multiple fill modes September 14, 2004
A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) define a
6789172 Cache and DMA with a global valid bit September 7, 2004
A digital system has at least one processor, with an associated multi-segment cache memory circuit. A single global validity circuit (VIG) is connected to the memory circuit and is operable to indicate if any segment of the multiple segments holds valid data. Block circuitry is opera
6772326 Interruptible an re-entrant cache clean range instruction August 3, 2004
A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in
6766421 Fast hardware looping mechanism for cache cleaning and flushing of cache entries corresponding t July 20, 2004
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associat
6760829 MMU descriptor having big/little endian bit to control the transfer data between devices July 6, 2004
A digital system is provided with a memory (506) shared by several initiator resources (540-550), wherein a portion of the initiator resources are big endian and another portion of the initiator resources are little endian. The memory is segregated into a set of regions by a memory m
6754781 Cache with DMA and dirty bits June 22, 2004
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plural
6751706 Multiple microprocessors with a shared cache June 15, 2004
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associat
6745293 Level 2 smartcache architecture supporting simultaneous multiprocessor accesses June 1, 2004
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associat
6742104 Master/slave processing system with shared translation lookaside buffer May 25, 2004
A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses .mu.TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the .mu.TLB and shared TLB, acce
6742103 Processing system with shared translation lookaside buffer May 25, 2004
A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses .mu.TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the .mu.TLB and shared TLB, acce
6728838 Cache operation based on range of addresses April 27, 2004
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (1806(n). Validity circuitry (VI) and dirty bit circuitry (DI) is connected to the memory circuit and is operable to indicate
6697916 Cache with block prefetch and DMA February 24, 2004
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plural
6684280 Task based priority arbitration January 27, 2004
A digital system and method of operation is provided in which several processors (1400, 1402, 1404) are connected to a shared resource (1432). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. Ar
6681297 Software controlled cache configuration based on average miss rate January 20, 2004
A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a level three (L3) physical memory. Each tag entry includes a task-ID qualifier field and a resource ID qualifier field. Data
6678797 Cache/smartcache with interruptible block prefetch January 13, 2004
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment memory circuit. Validity circuitry is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments hol
6606687 Optimized hardware cleaning function for VIVT data cache August 12, 2003
A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX counter (82) and a MIN register (84) define a range of cache locations which are dirty. During the hardware clean function,
6430664 Digital signal processor with direct and virtual addressing August 6, 2002
A DSP (10) accesses internal memory using physical addresses and has a internal MMU (19) which allows the DSP (10) to work with a large virtual address space mapped to an external memory (20). The MMU (19) performs the translation between a virtual address and the physical address associ
6412048 Traffic controller using priority and burst control for reducing access latency June 25, 2002
A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes ci
6369855 Audio and video decoder circuit and system April 9, 2002
An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM
6321299 Computer circuits, systems, and methods using partial cache cleaning November 20, 2001
A method (50) of operating a computing system (10). The computing system comprises a cache memory (12b), and the cache memory has a predetermined number of cache lines. First, the method, for a plurality of write addresses, writes data (64) to the cache memory at a location correspon
6310657 Real time window address calculation for on-screen display October 30, 2001
An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.
6253297 Memory control using memory state information for reducing access latency June 26, 2001
A memory controller circuit (18a) for coupling to a memory (24), where the memory has a plurality of rows. The memory controller circuit includes circuitry (28) for receiving signals representative of requests to access the memory. Given these signals, a first such signal representative
6226291 Transport stream packet parser system May 1, 2001
A transport stream parser system is provided that utilizes an intermediate buffer for containing packets after processing with an associated flag and then use a processor for further processing of packets selected by such flags.










 
 
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