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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lang; Steve
Address:
Stow, MA
No. of patents:
8
Patents:




Patent Number Title Of Patent Date Issued
7213087 Mechanism to control the allocation of an N-source shared buffer May 1, 2007
A method and apparatus for ensuring fair and efficient use of a shared memory buffer. A preferred embodiment comprises a shared memory buffer in a multi-processor computer system. Memory requests from a local processor are delivered to a local memory controller by a cache control unit an
7100096 Special encoding of known bad data August 29, 2006
A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the
7076597 Broadcast invalidate scheme July 11, 2006
A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to proces
6961781 Priority rules for reducing network message routing latency November 1, 2005
A system and method is disclosed for reducing network message passing latency in a distributed multiprocessing computer system that contains a plurality of microprocessors in a computer network, each microprocessor including router logic to route message packets prioritized in importance
6779142 Apparatus and method for interfacing a high speed scan-path with slow-speed test equipment August 17, 2004
A system for scan testing a device under test ("DUT") in which the clock speed of the DUT differs from test equipment. A plurality of scan-flops in the DUT form a scan-wheel, which defines a closed scan path. The Data bits in the scan path are shifted through a scan-wheel controller base
6751721 Broadcast invalidate scheme June 15, 2004
A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to proces
6738836 Scalable efficient I/O port protocol May 18, 2004
A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or mor
6662319 Special encoding of known bad data December 9, 2003
A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the me


 
 
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