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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lane; Richard H.
Address:
San Jose, CA
No. of patents:
3
Patents:












Patent Number Title Of Patent Date Issued
4746623 Method of making bipolar semiconductor device with wall spacer May 24, 1988
A method for fabricating a semiconductor device in which the base resistance is minimized to increase the speed of operation of the device. This is accomplished because the device made by the method makes it possible to form the base and emitter contacts next to each other laterally
4736271 Protection device utilizing one or more subsurface diodes and associated method of manufacture April 5, 1988
A protection device (14) for an integrated circuit (12) created on a semiconductor body (24 and 26) utilizes one or more semiconductor diodes (D.sub.L and/or D.sub.H) that have subsurface PN junctions (46 and/or 56) for preventing high-magnitude voltages, such as those generated by e
4381956 Self-aligned buried channel fabrication process May 3, 1983
A technique is described for the preparation of buried channels of arbitrary conductivity type in a semiconductor device or integrated circuit containing oxide moats in an epitaxial surface layer. By following a specific sequence of process steps, two mask layers are obtained from a










 
 
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