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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lamb; Joel D
Address:
Ft Collins, CO
No. of patents:
5
Patents:












Patent Number Title Of Patent Date Issued
7343479 Method and apparatus for implementing two architectures in a chip March 11, 2008
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstruc
6618801 Method and apparatus for implementing two architectures in a chip using bundles that contain mic September 9, 2003
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstruc
6542862 Determining register dependency in multiple architecture systems April 1, 2003
An apparatus and method for determining register dependency in multiple architecture system. The system includes a microprocessor emulating an emulated instruction set using a native instruction set where the microprocessor contains at least one register. An execution engine provides
5306962 Qualified non-overlapping clock generator to provide control lines with non-overlapping clock ti April 26, 1994
A clocking methodology for VLSI chips which uses global overlapping clocks, locally or remotely generated non-overlapping clocks, combined with pipeline control signals to generate signals which control the transfer gates of registers in a pipeline. The signals which control the transfer
5124572 VLSI clocking system using both overlapping and non-overlapping clocks June 23, 1992
A clocking methodology for VLSI chips which uses global overlapping clocks plus locally or remotely generated non-overlapping clocks. Two overlapping clocks and two non-overlapping clocks are thus available in each block of a chip for use as timing edges. The global overlapping clocks ar










 
 
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