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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Lai; Jiin
Address:
Taipei, TW
No. of patents:
33
Patents:












Patent Number Title Of Patent Date Issued
8270840 Backward compatible optical USB device September 18, 2012
An optical USB device includes an electro-optical converter configured to receive optical signals from an optical fiber and to convert them into first electrical signals and configured to receive second electrical signals and to convert them into optical signals for transmission to the
8234416 Apparatus interoperable with backward compatible optical USB device July 31, 2012
An apparatus configured to couple to a universal serial bus (USB) 3.0 connector. The apparatus includes a management controller configured to couple to the USB 3.0 connector. The management controller is configured to detect from behavior on the D+ and D- pins of the USB 3.0 connector
7805567 Chipset and northbridge with raid access September 28, 2010
A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID
7782313 Reducing power during idle state August 24, 2010
Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data,
7757031 Data transmission coordinating method and system July 13, 2010
A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maxi
7271578 Voltage monitoring circuit September 18, 2007
A voltage monitoring circuit is capable of being integrated into a chip and monitoring the voltage quality. It mainly uses a first waveshaper to receive a voltage signal of a voltage source to be measured, process it to a logic signal, and output to a first logic level transformer. A fir
7231560 Apparatus and method for testing motherboard having PCI express devices June 12, 2007
This invention discloses a method for testing at least one physical link on a motherboard associated with an on-board PCI Express device. A test card is connected to an input/output port on the motherboard, wherein the test card has a PCI Express test device. A test pattern is transmitte
7136955 Expansion adapter supporting both PCI and AGP device functions November 14, 2006
An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication
7082489 Data memory controller that supports data bus invert July 25, 2006
The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandw
7051148 Data transmission sequencing method associated with briding device and application system May 23, 2006
A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is
6948057 Memory modules storing therein boot codes and method and device for locating same September 20, 2005
A memory module storing therein boot codes, a core logic device capable of distinguishing such memory module from the other memory modules of the same module specification, and a method for realizing the boot codes from the memory module storing therein the boot codes are disclosed. All
6944730 Read/write scheduling apparatus of controller chip and method for the same September 13, 2005
A read/write scheduling apparatus of controller chip and method for the same. The read/write scheduling apparatus is used for arbitrating a plurality of read and write requests from a CPU to access a memory unit. The read request has higher priority in a host bandwidth limited case and
6941398 Processing method, chip set and controller for supporting message signaled interrupt September 6, 2005
A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrup
6820219 Integrated testing method for concurrent testing of a number of computer components through soft November 16, 2004
An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations,
6738880 Buffer for varying data access speed and system applying the same May 18, 2004
A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provi
6721833 Arbitration of control chipsets in bus transaction April 13, 2004
A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually
6694400 PCI system controller capable of delayed transaction February 17, 2004
A method of conducting delayed data transaction on a PCI system and its associated devices. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed
6687320 Phase lock loop (PLL) clock generator with programmable skew and frequency February 3, 2004
A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the
6684284 Control chipset, and data transaction method and signal transmission devices therefor January 27, 2004
A data transaction method between control chips. Data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in sequence according to read/write commands, by which the control chips can detect the stat
6571323 Memory-access management method and system for synchronous dynamic Random-Access memory or the l May 27, 2003
A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memo
6549964 Delayed transaction method and device used in a PCI system April 15, 2003
A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a
6546448 Method and apparatus for arbitrating access to a PCI bus by a plurality of functions in a multi- April 8, 2003
Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry
6490665 Memory-access management method and system for synchronous random-access memory or the like December 3, 2002
A memory-access management method and system is provided for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations.
6484281 Software-based simulation system capable of simulating the combined functionality of a north bri November 19, 2002
A software-based simulation system is provided, which can provide the combined functionality of a South Bridge test module and a North Bridge test module based solely on either one of the two modules, i.e., either the South Bridge test module or the North Bridge test module without h
6463013 Clock generating apparatus and method thereof October 8, 2002
A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are
6400197 Delay device having a delay lock loop and method of calibration thereof June 4, 2002
A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required dela
6278641 Method and apparatus capable of programmably delaying clock of DRAM August 21, 2001
An apparatus and method capable of programmably delaying a clock of a memory. The apparatus and method utilize the BIOS, external electric switches or other logic devices to selectively delay the clock of the DRAM and/or the internal clock of the north bridge, by which the DRAM has e
6269430 Method for controlling a process of writing data sent by a central processing unit to a memory b July 31, 2001
A method for a CPU interface to control a writing process that writes data sent from a CPU to a memory. The CPU interface controls the writing process through steps mainly including receiving a write request and data from a CPU, sending a dummy request to the memory control circuit of th
6233528 Method and device for signal testing May 15, 2001
A signal-testing device used with a tester for testing a first signal and a second signal includes a selected signal generator receiving first signal and second signal for generating a selected signal the state of which is changed when first signal and second signal are in specific state
6202167 Computer chip set for computer mother board referencing various clock rates March 13, 2001
A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other c
6079027 Computer chip set for computer mother board referencing various clock rates June 20, 2000
A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other c
6031752 Installation for providing constant loading in memory slot February 29, 2000
An installation inside a memory slot for providing a constant loading to an external signaling line with or without the insertion of a memory module into a memory slot. The installation operates by supplying a load element whose loading effect is roughly equivalent to the loading effect
6020774 Gated clock tree synthesis method for the logic design February 1, 2000
A gated clock tree synthesis (CTS) method is provided for the purpose of synthesizing a gate array logic circuit to allow optimal topological arrangement of the gate array on the logic circuit. This in turn allows the logic circuit to operate more efficiently. The logic circuit includes










 
 
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