| Patent Number |
Title Of Patent |
Date Issued |
| RE37753 |
Semiconductor memory device and read and write methods thereof |
June 18, 2002 |
| A semiconductor memory device includes input/output circuitry capable of operating in sync with an externally provided I/O clock signal. A data in buffer and a data out buffer provide for serial to parallel conversion of write data and, conversely, parallel to serial conversion of read d |
| 7539826 |
System, device, and method for improved mirror mode operation of a semiconductor memory device |
May 26, 2009 |
| By using the combination of a pre-existing command signal that is common to two memory devices and a non-shared command signal that is applied individually to each of the devices, embodiments of the invention may operate in a mirror mode, thereby preventing unwanted signal degradation |
| 6525417 |
Integrated circuits having reduced step height by using dummy conductive lines |
February 25, 2003 |
| A step height between first and second elevated conductive lines that are laterally spaced apart on an integrated circuit substrate may be reduced by forming a dummy conductive line beneath the second conductive line, to further elevate the second conductive line on the integrated circui |
| 6486651 |
Integrated circuit devices having a delay locked loop that is configurable for high-frequency op |
November 26, 2002 |
| Integrated circuit devices and methods of operating same include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrat |
| 6372626 |
Method of reducing step heights in integrated circuits by using dummy conductive lines, and inte |
April 16, 2002 |
| A step height between first and second elevated conductive lines that are laterally spaced apart on an integrated circuit substrate may be reduced by forming a dummy conductive line beneath the second conductive line, to further elevate the second conductive line on the integrated circui |
| 6304500 |
Integrated circuit memory devices having data input and output lines extending in the column dir |
October 16, 2001 |
| Integrated circuit memory devices having data input and output lines in a column direction and circuits and methods for repairing faulty cells are provided. A column select line according to the present invention extends along a row direction. Data input and output lines extend along a c |
| 6151263 |
Integrated circuit memory devices having data input and output lines extending along the column |
November 21, 2000 |
| Integrated circuit memory devices having data input and output lines in a column direction are provided. A column select line according to the present invention extends along a row direction. Data input and output lines extend along a column direction. Thus, an increase of layout area |
| 6141271 |
Circuits for testing memory devices having direct access test mode and methods for testing the s |
October 31, 2000 |
| An integrated circuit memory device includes a test mode. Data is written to and read from the integrated circuit memory device in the test mode. The integrated circuit memory device includes a memory array that includes memory cells that store data. A test control circuit generates cont |
| 6078536 |
Packet type integrated circuit memory devices having pins assigned direct test mode and associat |
June 20, 2000 |
| An integrated circuit memory device and method including a direct mode assigns internal data and address signals to separate pins. In particular, a plurality of first pins is assigned to the plurality of internal data signals that provide the data to the memory array in direct test mode. |
| 6046947 |
Integrated circuit memory devices having direct access mode test capability and methods of testi |
April 4, 2000 |
| Integrated circuit memory devices include test mode control circuits to more efficiently route test data to a fewer number of output pins during test mode operation. The memory device may include first and second memory arrays having first and second pluralities of data lines electricall |
| 5986953 |
Input/output circuits and methods for testing integrated circuit memory devices |
November 16, 1999 |
| Integrated circuit memory devices include a plurality of pads that receive signals from external of the memory device and a plurality of data buses, a respective one of which is operatively connected to a respective one of the plurality of pads. A plurality of multiplexers is provided, a |
