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Inventor:
Kyo; Shorin
Address:
Tokyo, JP
No. of patents:
8
Patents:












Patent Number Title Of Patent Date Issued
8190856 Data transfer network and control apparatus for a system with an array of processing elements ea May 29, 2012
A processor of SIMD/MIMD dual mode architecture comprises common controlled first processing elements, self-controlled second processing elements and a pipelined (ring) network connecting the first PEs and the second PEs sequentially. An access controller has access control lines, ea
8131978 Restoring plural instructions for same cycle execution from partial instructions and combined su March 6, 2012
An original first instruction word (I1) to an original third instruction word (I3) include a bit field (L11) and a bit field (L12) to a bit field (L31) and a bit field (L32). An information word (IW) includes a set of some of bit fields belonging to a plurality of instruction words execu
8112613 Selecting broadcast SIMD instruction or cached MIMD instruction stored in local memory of one of February 7, 2012
Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N/S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inhere
8051273 Supplying instruction stored in local memory configured as cache to peer processing elements in November 1, 2011
Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N/S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inhere
7853775 Processing elements grouped in MIMD sets each operating in SIMD mode by controlling memory porti December 14, 2010
Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N/S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inhere
7783861 Data reallocation among PEs connected in both directions to respective PEs in adjacent blocks by August 24, 2010
When an instruction code "MVLR" is sent from a control processor in a PE having a mask register MR in operation setting, when the direction register F is ON, if a counter and transfer result storing buffer T is .gtoreq.M, a value of T-M is stored in buffer T, and if T is less than M,
7509634 SIMD instruction sequence generating program, SIMD instruction sequence generating method and ap March 24, 2009
A translator receives a source code that is described using a process designation (such as a line-by-line process designation, a line data extraction designation, and a broadcast designation) to be performed on line data of an image on a line by line basis, parses and optimizes the s
7400781 Symmetric type image filter processing apparatus and program and method therefor July 15, 2008
A symmetric type image filter processing apparatus having a symmetric type image filter composed of symmetric kernel coefficients, in which SIMD commands are utilized efficiently for making the filtering processes high speed, is provided. The symmetric type image filter processing appara










 
 
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