A multi-chip semiconductor memory device includes of a plurality of memory chips sharing a predetermined chip enable signal. Each of the plurality of memory chips includes an active internal power supply generation circuit configured to convert an external power supply voltage into an
A high voltage generation circuit for use with a semiconductor memory device includes a plurality of high voltage generation units and a control circuit. The high voltage generation units generate high voltages having different voltage levels in response to corresponding clock signal
In one aspect, a programming method is provided for a non-volatile semiconductor memory device which includes a plurality of electrically programmable and erasable memory cells, and transmission transistors for providing predetermined voltages to the memory cells. The method includes
A flash memory device may include: a plurality of main bit lines; a plurality of redundant bit lines; a plurality of first page buffers respectively organized as a plurality of first page buffer groups which are connected to main bit lines; a plurality of second page buffers respecti
