| Patent Number |
Title Of Patent |
Date Issued |
| 7599228 |
Flash memory device having increased over-erase correction efficiency and robustness against dev |
October 6, 2009 |
| A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain re |
| 7561471 |
Cycling improvement using higher erase bias |
July 14, 2009 |
| Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cell |
| 7553727 |
Using implanted poly-1 to improve charging protection in dual-poly process |
June 30, 2009 |
| The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the |
| 7319615 |
Ramp gate erase for dual bit flash memory |
January 15, 2008 |
| A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value tha |
| 7154141 |
Source side programming |
December 26, 2006 |
| A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characte |
| 7079424 |
Methods and systems for reducing erase times in flash memory devices |
July 18, 2006 |
| A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-prog |
| 6894925 |
Flash memory cell programming method and system |
May 17, 2005 |
| A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases |
| 6747900 |
Memory circuit arrangement for programming a memory cell |
June 8, 2004 |
| A memory circuit for programming a target cell is disclosed. According to one embodiment, the memory circuit comprises the target cell having a drain terminal connected to a bit line. A drain voltage is coupled to the bit line and supplies a voltage greater than a ground voltage, while a |
| 6347054 |
Method of operating flash memory |
February 12, 2002 |
| A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes lowering the control gate to a potential |
| 6043123 |
Triple well flash memory fabrication process |
March 28, 2000 |
| A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the |
| 5981994 |
Method and semiconductor circuit for maintaining integrity of field threshold voltage requiremen |
November 9, 1999 |
| A method for maintaining a high field threshold voltage in a plurality of transistors of reduced size in a periphery region of a Flash EPROM semiconductor circuit includes forming a first polysilicon layer as a floating poly in a predetermined number of transistors of the plurality of |
| 5882985 |
Reduction of field oxide step height during semiconductor fabrication |
March 16, 1999 |
| A method for reducing the steep step at the edge of a locally oxidized, field oxide boundary region as a result of using the local oxidation of silicon (LOCOS) method to isolate the active regions of a semiconductor wafer. The reduction is carried out by applying a planarizing layer to t |
| 5652155 |
Method for making semiconductor circuit including non-ESD transistors with reduced degradation d |
July 29, 1997 |
| A method for reducing encroachment of an impurity implant into a channel region in a non-ESD transistor in a semiconductor circuit, the non-ESD transistor receiving both first and second implant dopants, and the circuit including a plurality of ESD transistors includes forming the ESD |
| 5521867 |
Adjustable threshold voltage conversion circuit |
May 28, 1996 |
| A flash EPROM circuit for providing a tight erase threshold voltage distribution. The circuit includes an array of memory cells having gates, sources and drains. Bit lines are coupled to the drains of a column of cells in the memory array. A plurality of word lines are each coupled to |
