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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Kurachi; Ikuo
Address:
Tokyo, JP
No. of patents:
11
Patents:












Patent Number Title Of Patent Date Issued
7776691 Semiconductor memory device and manufacturing method for semiconductor device August 17, 2010
The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory. The solution is a manufacturing method for semiconductor memory device including a process for
7732783 Ultraviolet light monitoring system June 8, 2010
An ultraviolet light monitoring system includes first and second electrodes, an evaluation subject film and a power source. The first and second electrodes are opposingly disposed and attract holes which are generated in accordance with irradiation of ultraviolet light. The evaluatio
7714370 Semiconductor storage device having an SOI structure May 11, 2010
A semiconductor storage device includes: a MOSFET formed on an SOI layer of the transistor forming region; and a MOS capacitor formed on the SOI layer of the capacitor forming region. The MOSFET includes: a gate insulating film formed; a floating gate electrode; a source layer and a
7462896 Semiconductor memory device and manufacturing method for semiconductor memory device December 9, 2008
The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory. The solution is a manufacturing method for semiconductor memory device including a process for
7199030 Method of manufacturing semiconductor device April 3, 2007
An impurity is ion-implanted with a silicon nitride film formed on a silicon substrate as a mask film to form a source/drain layer of a MOS transistor. Heat treatment for activating the impurity is done as it is without removing the silicon nitride film to thereby produce heat treatm
6507521 Semiconductor memory system January 14, 2003
A pulse voltage with its frequency set at approximately 1 MHz and achieving a level of approximately 1V on the high level side and a level of -5.about.-7V on the low level side is applied to the P-type well 123. When 1V is applied to a P-type well 123, the resulting forward bias causes
6434047 Semiconductor memory system August 13, 2002
A pulse voltage with its frequency set at approximately 1 MHz and achieving a level of approximately 1V on the high level side and a level of -5.about.-7V on the low level side is applied to the P-type well 123. When 1V is applied to a P-type well 123, the resulting forward bias causes
6383866 Semiconductor device and manufacturing method thereof May 7, 2002
A Si.sub.3 N.sub.4 film and a side wall are provided on an electrode to obtain a Cs capacitor capable of enlarging an area of a memory cell contact of a DRAM, and a hole if formed penetrating an inter-layer film by a selective etching process. The Si.sub.3 N.sub.4 film and the side wall
6356479 Semiconductor memory system March 12, 2002
A pulse voltage with its frequency set at approximately 1 MHz and achieving a level of approximately 1V on the high level side and a level of -5.about.-7V on the low level side is applied to the P-type well 123. When 1V is applied to a P-type well 123, the resulting forward bias causes
5856694 Semiconductor device having protection device for preventing the electrostatic breakdown of outp January 5, 1999
A semiconductor device of the present invention includes an integrated circuit formed on a first conduction-type semiconductor substrate, an output buffer circuit for outputting a signal obtained from the integrated circuit, a protection circuit for protecting the output buffer circuit a
5739571 Semiconductor device having protection device for preventing the electrostatic breakdown of outp April 14, 1998
A semiconductor device of the present invention includes an integrated circuit formed on a first conduction-type semiconductor substrate, an output buffer circuit for outputting a signal obtained from the integrated circuit, a protection circuit for protecting the output buffer circuit a










 
 
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