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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Kuo; Ming-Hong
Address:
Ping-Tung, TW
No. of patents:
7
Patents:












Patent Number Title Of Patent Date Issued
6261923 Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local in July 17, 2001
A method for forming planarized isolation using a nitride hard mask and two CMP steps is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride and pad oxide layers are etched through where they are not covered
6184081 Method of fabricating a capacitor under bit line DRAM structure using contact hole liners February 6, 2001
A process for fabricating a DRAM capacitor structure, in which the capacitor upper plate structure is defined during the formation of bit line contact hole opening, and substrate contact hole opening procedure, eliminating the need for a specific upper plate, photolithographic masking
6133599 Design and a novel process for formation of DRAM bit line and capacitor node contacts October 17, 2000
A process for fabricating a DRAM cell has been developed, in which two interlaced patterns, each comprised of capacitor node contact holes and bit line contact holes, are independently created, each using a specific photolithographic mask, and a specific photolithographic procedure. The
6060348 Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technolog May 9, 2000
A method for forming planarized isolation by combining LOCOS and STI isolation processes is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride layer and pad oxide layer are etched through where they are not
6017813 Method for fabricating a damascene landing pad January 25, 2000
A process for forming a damascene landing pad structure, used to connect a bit line structure, of a semiconductor memory device, to an underlying source and drain region, of a transfer gate transistor, has been developed. The process features the formation of a dual shaped, landing p
6008085 Design and a novel process for formation of DRAM bit line and capacitor node contacts December 28, 1999
A process for fabricating a DRAM cell has been developed, in which two interlaced patterns, each comprised of capacitor node contact holes and bit line contact holes, are independently created, each using a specific photolithographic mask, and a specific photolithographic procedure. The
5658822 Locos method with double polysilicon/silicon nitride spacer August 19, 1997
An improved local oxidation of silicon (LOCOS) method with recessed silicon substrate and double polysilicon/silicon nitride spacer is disclosed. The present invention includes forming a pad oxide layer on a semiconductor substrate and then forming a first silicon nitride layer on the pa










 
 
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