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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Kuo; Di-Son
Address:
Hsinchu, TW
No. of patents:
102
Patents:


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Patent Number Title Of Patent Date Issued
7417278 Method to increase coupling ratio of source to floating gate in split-gate flash August 26, 2008
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
7001809 Method to increase coupling ratio of source to floating gate in split-gate flash February 21, 2006
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6803625 Method with trench source to increase the coupling of source to floating gate in split gate flas October 12, 2004
A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is
6724036 Stacked-gate flash memory cell with folding gate and increased coupling ratio April 20, 2004
A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the
6674118 PIP capacitor for split-gate flash process January 6, 2004
A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, res
6667509 Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split December 23, 2003
A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory. This is accomplished in two embodiments where in the first, fluorine is implanted in the first polysilicon layer to form the floating gate. It is disclos
6624025 Method with trench source to increase the coupling of source to floating gate in split gate flas September 23, 2003
A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is
6583466 Vertical split gate flash memory device in an orthogonal array of rows and columns with devices June 24, 2003
A vertical transistor memory device includes FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region FOX regions are formed between the rows.
6573555 Source side injection programming and tip erasing P-channel split gate flash memory cell June 3, 2003
A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a con
6559501 Method for forming split-gate flash cell for salicide and self-align contact May 6, 2003
A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an
6544828 Adding a poly-strip on isolation's edge to improve endurance of high voltage NMOS on EEPROM April 8, 2003
A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is
6538277 Split-gate flash cell March 25, 2003
A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over
6538276 Split gate flash memory device with shrunken cell and source line array dimensions March 25, 2003
A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate
6534821 Structure with protruding source in split-gate flash March 18, 2003
A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide.
6509603 P-channel EEPROM and flash EEPROM devices January 21, 2003
A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer,
6504206 Split gate flash cell for multiple storage January 7, 2003
In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into the semiconductor substrate and
6495880 Method to fabricate a flash memory cell with a planar stacked gate December 17, 2002
A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon l
6483159 Undoped polysilicon as the floating-gate of a split-gate flash cell November 19, 2002
A split gate EEPROM memory device formed on a doped silicon semi-conductor substrate starting with an initial oxide layer with an undoped first polysilicon layer formed thereon. A polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide
6479859 Split gate flash memory with multiple self-alignments November 12, 2002
A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The
6468863 Split gate field effect transistor (FET) device employing dielectric barrier layer and method fo October 22, 2002
Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first
6465841 Split gate flash memory device having nitride spacer to prevent inter-poly oxide damage October 15, 2002
A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers s
6465836 Vertical split gate field effect transistor (FET) device October 15, 2002
Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field e
6455887 Nonvolatile devices with P-channel EEPROM device as injector September 24, 2002
An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region
6441429 Split-gate flash memory device having floating gate electrode with sharp peak August 27, 2002
A split gate electrode MOS FET device includes a tunnel oxide layer formed over a semiconductor substrate. Over the tunnel oxide layer, a doped first polysilicon layer is formed with a top surface. A native oxide which forms over the doped first polysilicon layer may have been removed as
6437397 Flash memory cell with vertically oriented channel August 20, 2002
A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silico
6420233 Split gate field effect transistor (FET) device employing non-linear polysilicon floating gate e July 16, 2002
Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a perip
6417049 Split gate flash cell for multiple storage July 9, 2002
In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into the semiconductor substrate and
6417046 Modified nitride spacer for solving charge retention issue in floating gate memory cell July 9, 2002
A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the
6410957 Method of forming poly tip to improve erasing and programming speed in split gate flash June 25, 2002
A method is disclosed for forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve the erasing and programming speed of the cell. The method involves the use of an oxide other than the poly oxide that is conventionally employed in formin
6403494 Method of forming a floating gate self-aligned to STI on EEPROM June 11, 2002
A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory
6396112 Method of fabricating buried source to shrink chip size in memory array May 28, 2002
A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having
6391719 Method of manufacture of vertical split gate flash memory device May 21, 2002
A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form
6387757 Sacrificial self aligned spacer layer ion implant mask method for forming a split gate field eff May 14, 2002
Within a method for fabricating a split gate field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, there is employed a sacrificial self aligned spacer layer which defines a control gate electrode channel within the split gate field effect
6380583 Method to increase coupling ratio of source to floating gate in split-gate flash April 30, 2002
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6380035 Poly tip formation and self-align source process for split-gate flash cell April 30, 2002
A novel method of forming a polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notched nitride layer over the tip. At the same time, a method of forming a self-aligned source (SAS) line i
6355527 Method to increase coupling ratio of source to floating gate in split-gate flash March 12, 2002
A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed ove
6333228 Method to improve the control of bird's beak profile of poly in split gate flash December 25, 2001
A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing pro
6326662 Split gate flash memory device with source line December 4, 2001
A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate elect
6326660 Method to improve the capacity of data retention and increase the coupling ratio of source to fl December 4, 2001
A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between th
6312989 Structure with protruding source in split-gate flash November 6, 2001
A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide.
6309928 Split-gate flash cell October 30, 2001
A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F--N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over
6297099 Method to free control tunneling oxide thickness on poly tip of flash October 2, 2001
A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is
6284596 Method of forming split-gate flash cell for salicide and self-align contact September 4, 2001
A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an
6277686 PIP capacitor for split-gate flash process August 21, 2001
A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, res
6251744 Implant method to improve characteristics of high voltage isolation and high voltage breakdown June 26, 2001
A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is
6249454 Split-gate flash cell for virtual ground architecture June 19, 2001
In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual
6246089 P-channel EEPROM devices June 12, 2001
A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer,
6246075 Test structures for monitoring gate oxide defect densities and the plasma antenna effect June 12, 2001
An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashi
6245685 Method for forming a square oxide structure or a square floating gate structure without rounding June 12, 2001
A method for forming a square oxide structure or a square floating gate without a rounding effect at its corners. A first dielectric layer is formed on a pad layer for a square oxide structure or a polysilicon layer overlying a gate oxide layer for a floating gate, and a second dielectri
6242308 Method of forming poly tip to improve erasing and programming speed split gate flash June 5, 2001
A method is disclosed for forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve the erasing and programming speed of the cell. The method involves the use of an oxide other than the poly oxide that is conventionally employed in formin
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