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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Kunitomo; Masato
Address:
Ome, JP
No. of patents:
4
Patents:












Patent Number Title Of Patent Date Issued
6746913 Method of manufacturing semiconductor integrated circuit device comprising a memory cell and a c June 8, 2004
A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450.degree. C. to 700.degree. C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer
6720603 CAPACITOR STRUCTURE AND A SEMICONDUCTOR DEVICE WITH A FIRST METAL LAYER, A SECOND METAL SILICIDE April 13, 2004
A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented
6534375 METHOD OF FORMING A CAPACITOR IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING A METAL SILICON March 18, 2003
A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented
6235572 Method of making a memory cell having two layered tantalum oxide films May 22, 2001
A semiconductor device includes a DRAM having a memory cell constructed by an information storage capacitor C which is comprised of a lower electrode 54 made of a ruthenium film and an upper electrode 62 made of a capacity insulating film 61 and a titanium nitride film and which is conne










 
 
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