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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Kueper; Terrance Wayne
Address:
Rochester, MN
No. of patents:
14
Patents:












Patent Number Title Of Patent Date Issued
7935629 Semiconductor scheme for reduced circuit area in a simplified process May 3, 2011
An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created
7734444 Systems and arrangements to assess thermal performance June 8, 2010
Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an
7696565 FinFET body contact structure April 13, 2010
A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin p
7626220 Semiconductor scheme for reduced circuit area in a simplified process December 1, 2009
An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created
7338818 Systems and arrangements to assess thermal performance March 4, 2008
Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an
7317605 Method and apparatus for improving performance margin in logic paths January 8, 2008
An apparatus and method is disclosed for improving timing margins of logic paths on a semiconductor chip. Typical logic embodiments, such as CMOS (Complementary Metal Oxide Semiconductor), have path delays that become shorter as supply voltage is increased. Embodiments of the present
7317217 Semiconductor scheme for reduced circuit area in a simplified process January 8, 2008
An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created
7241649 FinFET body contact structure July 10, 2007
A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin p
7227183 Polysilicon conductor width measurement for 3-dimensional FETs June 5, 2007
An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon "fins". A first resisto
7184924 Method, apparatus and computer program product for implementing thermal integrity screening February 27, 2007
A method, apparatus and computer program product are provided for implementing thermal integrity screening. Predefined processor module temperature data are obtained and processed. An initial thermal calibration is performed to record a predefined processor resistance with no power a
7009905 Method and apparatus to reduce bias temperature instability (BTI) effects March 7, 2006
Methods and apparatus are disclosed that allow an electronic system implemented with field effect transistors (FETs) to reduce threshold voltage shifts caused by bias temperature instability (BTI). BTI caused VT shifts accumulate when an FET is in a particular voltage stress conditio
6879177 Method and testing circuit for tracking transistor stress degradation April 12, 2005
A method and testing circuit are provided for tracking transistor stress degradation. A first array of P-channel field effect transistors (PFETs) is connected in parallel. The first array of PFETs is stressed by applying a low gate input and a high source and a high drain to the PFETs du
6774734 Ring oscillator circuit for EDRAM/DRAM performance monitoring August 10, 2004
Circuitry and methods are disclosed for quantitatively characterizing the delay of Embedded Dynamic Random Access Memory (EDRAM) and Dynamic Random Access Memory (DRAM). The performance critical portion of the memory is placed in a ring oscillator designed such that the delay through the
6198316 CMOS off-chip driver circuit March 6, 2001
An improved off-chip driver circuit is disclosed which will properly transition from an active mode to a high impedance mode. The circuit includes first and second input nodes for receiving a first and second input signal respectively. An input composite transmission gate including a










 
 
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