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Inventor: Kudo; Mamoru
Address: Kanagawa, JP
No. of patents: 7
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 7578676 |
Semiconductor device |
August 25, 2009 |
| A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first |
| 7554186 |
Semiconductor device |
June 30, 2009 |
| A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet dispose |
| 7469367 |
Phase error determination method and digital phase-locked loop system |
December 23, 2008 |
| In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then run-length counted with a virtual channel clock so as to extr |
| 7351068 |
Semiconductor device |
April 1, 2008 |
| A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first |
| 7342986 |
Digital PLL device |
March 11, 2008 |
| A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of |
| 7315968 |
Phase error determination method and digital phase-locked loop system |
January 1, 2008 |
| In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-len |
| 6992958 |
Phase-locked loop circuit for reproducing a channel clock |
January 31, 2006 |
| In PLL circuits for reproducing a channel clock in synchronism with data read from a disk-shaped recording medium driven for rotation, the frequency dividing ratio of frequency dividers provided in desired signal paths is made changeable according to the reproduced signal format of a |
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